mediatek/mt76/mt76_connac2_mac.h

1 /* SPDX-License-Identifier: ISC */
23 	MT_HIF0 = 0x0,
25 	MT_LMAC_AC00 = 0x0,
29 	MT_LMAC_ALTX0 = 0x10,
36 	MT_TXS_MPDU_FMT = 0,
40 #define MT_TX_FREE_MSDU_CNT		GENMASK(9, 0)
42 #define MT_TX_FREE_COUNT		GENMASK(12, 0)
43 /* 0: success, others: dropped */
46 #define MT_TX_FREE_PAIR			BIT(31)
48 #define MT_TX_FREE_RATE			GENMASK(13, 0)
50 #define MT_TXD0_Q_IDX			GENMASK(31, 25)
53 #define MT_TXD0_TX_BYTES		GENMASK(15, 0)
55 #define MT_TXD1_LONG_FORMAT		BIT(31)
65 #define MT_TXD1_WLAN_IDX		GENMASK(9, 0)
67 #define MT_TXD2_FIX_RATE		BIT(31)
81 #define MT_TXD2_SUB_TYPE		GENMASK(3, 0)
83 #define MT_TXD3_SN_VALID		BIT(31)
95 #define MT_TXD3_NO_ACK			BIT(0)
97 #define MT_TXD4_PN_LOW			GENMASK(31, 0)
99 #define MT_TXD5_PN_HIGH			GENMASK(31, 16)
105 #define MT_TXD5_PID			GENMASK(7, 0)
107 #define MT_TXD6_TX_IBF			BIT(31)
117 #define MT_TXD6_BW			GENMASK(1, 0)
119 #define MT_TXD7_TXD_LEN			GENMASK(31, 30)
128 #define MT_TXD7_TX_TIME			GENMASK(9, 0)
131 #define MT_TXD8_L_SUB_TYPE		GENMASK(3, 0)
138 /* VHT/HE only use bits 0-3 */
139 #define MT_TX_RATE_IDX			GENMASK(5, 0)
141 #define MT_TXS0_FIXED_RATE		BIT(31)
158 #define MT_TXS0_TX_RATE			GENMASK(13, 0)
160 #define MT_TXS1_SEQNO			GENMASK(31, 20)
163 #define MT_TXS1_TX_POWER_DBM		GENMASK(7, 0)
165 #define MT_TXS2_BF_STATUS		GENMASK(31, 30)
169 #define MT_TXS2_TX_DELAY		GENMASK(15, 0)
171 #define MT_TXS3_PID			GENMASK(31, 24)
172 #define MT_TXS3_ANT_ID			GENMASK(23, 0)
174 #define MT_TXS4_TIMESTAMP		GENMASK(31, 0)
177 #define MT_TXS5_MPDU_TX_BYTE		GENMASK(22, 0)
178 #define MT_TXS5_MPDU_TX_CNT		GENMASK(31, 23)
180 #define MT_TXS6_MPDU_FAIL_CNT		GENMASK(31, 23)
181 #define MT_TXS7_MPDU_RETRY_BYTE		GENMASK(22, 0)
182 #define MT_TXS7_MPDU_RETRY_CNT		GENMASK(31, 23)
185 #define MT_RXD0_LENGTH			GENMASK(15, 0)
187 #define MT_RXD0_PKT_TYPE		GENMASK(31, 27)
194 #define MT_RXD1_NORMAL_WLAN_IDX		GENMASK(9, 0)
210 #define MT_RXD1_NORMAL_SEC_DONE		BIT(31)
213 #define MT_RXD2_NORMAL_BSSID		GENMASK(5, 0)
230 #define MT_RXD2_NORMAL_BF_REPORT	BIT(31)
233 #define MT_RXD4_NORMAL_PAYLOAD_FORMAT	GENMASK(1, 0)
234 #define MT_RXD4_FIRST_AMSDU_FRAME	GENMASK(1, 0)
236 #define MT_RXD4_LAST_AMSDU_FRAME	BIT(0)
244 #define MT_RXD3_NORMAL_PF_STS		GENMASK(31, 30)
249 #define MT_RXD3_NORMAL_RXV_SEQ		GENMASK(7, 0)
252 #define MT_RXD3_NORMAL_U2M		BIT(0)
253 #define MT_RXD3_NORMAL_HTC_VLD		BIT(0)
266 #define MT_RXD3_NORMAL_VLAN2ETH		BIT(31)
269 #define MT_RXD6_FRAME_CONTROL		GENMASK(15, 0)
270 #define MT_RXD6_TA_LO			GENMASK(31, 16)
272 #define MT_RXD7_TA_HI			GENMASK(31, 0)
274 #define MT_RXD8_SEQ_CTRL		GENMASK(15, 0)
275 #define MT_RXD8_QOS_CTL			GENMASK(31, 16)
277 #define MT_RXD9_HT_CONTROL		GENMASK(31, 0)
279 /* P-RXV DW0 */
280 #define MT_PRXV_TX_RATE			GENMASK(6, 0)
286 #define MT_PRXV_HE_RU_ALLOC_L		GENMASK(31, 28)
295 /* P-RXV DW1 */
296 #define MT_PRXV_RCPI3			GENMASK(31, 24)
299 #define MT_PRXV_RCPI0			GENMASK(7, 0)
300 #define MT_PRXV_HE_RU_ALLOC_H		GENMASK(3, 0)
302 /* C-RXV */
303 #define MT_CRXV_HT_STBC			GENMASK(1, 0)
311 #define MT_CRXV_HE_UPLINK		BIT(31)
313 #define MT_CRXV_HE_RU0			GENMASK(7, 0)
316 #define MT_CRXV_HE_RU3			GENMASK(31, 24)
325 #define MT_CRXV_HE_BSS_COLOR		GENMASK(5, 0)
331 #define MT_CRXV_FOE_LO		GENMASK(31, 19)
332 #define MT_CRXV_FOE_HI		GENMASK(6, 0)
338 #define MT_CT_INFO_APPLY_TXD		BIT(0)
346 	MT_TX_MCU_PORT_RX_Q0 = 0x20,
350 	MT_TX_MCU_PORT_RX_FWDL = 0x3e