realtek/rtw89/txrx.h

1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
12 #define DATA_RATE_NOT_HT_IDX_MASK	GENMASK(3, 0)
13 #define DATA_RATE_MODE_NON_HT		0x0
14 #define DATA_RATE_HT_IDX_MASK		GENMASK(4, 0)
15 #define DATA_RATE_HT_IDX_MASK_V1	GENMASK(4, 0)
16 #define DATA_RATE_MODE_HT		0x1
19 #define DATA_RATE_VHT_HE_IDX_MASK	GENMASK(3, 0)
21 #define DATA_RATE_MCS_MASK_V1		GENMASK(4, 0)
22 #define DATA_RATE_MODE_VHT		0x2
23 #define DATA_RATE_MODE_HE		0x3
24 #define DATA_RATE_MODE_EHT		0x4
28 	if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)  in rtw89_get_data_rate_mode()
41 	if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)  in rtw89_get_data_ht_mcs()
49 	if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)  in rtw89_get_data_mcs()
62 	if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)  in rtw89_get_data_nss()
68 /* TX WD BODY DWORD 0 */
69 #define RTW89_TXWD_BODY0_WP_OFFSET GENMASK(31, 24)
79 #define RTW89_TXWD_BODY0_HW_SSN_MODE GENMASK(1, 0)
82 #define RTW89_TXWD_BODY1_ADDR_INFO_NUM GENMASK(31, 26)
83 #define RTW89_TXWD_BODY1_PAYLOAD_ID GENMASK(31, 16)
85 #define RTW89_TXWD_BODY1_SEC_TYPE GENMASK(3, 0)
91 #define RTW89_TXWD_BODY2_TXPKT_SIZE GENMASK(13, 0)
96 #define RTW89_TXWD_BODY3_SW_SEQ GENMASK(11, 0)
99 #define RTW89_TXWD_BODY4_SEC_IV_L1 GENMASK(31, 24)
103 #define RTW89_TXWD_BODY5_SEC_IV_H5 GENMASK(31, 24)
106 #define RTW89_TXWD_BODY5_SEC_IV_H2 GENMASK(7, 0)
111 #define RTW89_TXWD_BODY7_USE_RATE_V1 BIT(31)
116 /* TX WD INFO DWORD 0 */
131 #define RTW89_TXWD_INFO1_MAX_AGGNUM GENMASK(7, 0)
138 #define RTW89_TXWD_INFO2_SEC_CAM_IDX GENMASK(7, 0)
144 #define RTW89_TXWD_INFO4_HW_RTS_EN BIT(31)
148 /* TX WD BODY DWORD 0 */
149 #define BE_TXD_BODY0_EN_HWSEQ_MODE GENMASK(1, 0)
166 #define BE_TXD_BODY0_HCI_SEQNUM_MODE BIT(31)
169 #define BE_TXD_BODY1_DMA_TXAGG_NUM GENMASK(6, 0)
176 #define BE_TXD_BODY1_ADDR_INFO_NUM GENMASK(31, 26)
179 #define BE_TXD_BODY2_TXPKTSIZE GENMASK(13, 0)
185 #define BE_TXD_BODY2_MACID GENMASK(31, 24)
188 #define BE_TXD_BODY3_WIFI_SEQ GENMASK(11, 0)
198 #define BE_TXD_BODY3_BAND1_SU_RTY_V1 BIT(31)
201 #define BE_TXD_BODY4_TXDESC_CHECKSUM GENMASK(15, 0)
203 #define BE_TXD_BODY4_SEC_IV_L1 GENMASK(31, 24)
206 #define BE_TXD_BODY5_SEC_IV_H2 GENMASK(7, 0)
209 #define BE_TXD_BODY5_SEC_IV_H5 GENMASK(31, 24)
212 #define BE_TXD_BODY6_MU_TC GENMASK(4, 0)
221 #define BE_TXD_BODY6_RU_POS GENMASK(31, 24)
224 #define BE_TXD_BODY7_RTS_TC GENMASK(5, 0)
232 #define BE_TXD_BODY7_USERATE_SEL BIT(31)
234 /* TX WD INFO DWORD 0 */
235 #define BE_TXD_INFO0_MBSSID GENMASK(3, 0)
245 #define BE_TXD_INFO0_ACK_CH_INFO BIT(31)
248 #define BE_TXD_INFO1_MAX_AGG_NUM GENMASK(7, 0)
255 #define BE_TXD_INFO1_SW_DEFINE GENMASK(31, 28)
258 #define BE_TXD_INFO2_SEC_CAM_IDX GENMASK(7, 0)
266 #define BE_TXD_INFO2_SIFS_TX_V1 BIT(31)
269 #define BE_TXD_INFO3_SPE_PKT GENMASK(3, 0)
283 #define BE_TXD_INFO3_FORCE_BSS_CLR BIT(31)
286 #define BE_TXD_INFO4_PUNCTURE_PATTERN GENMASK(15, 0)
294 #define BE_TXD_INFO4_HW_RTS_EN BIT(31)
297 #define BE_TXD_INFO5_SR_RATE_V1 GENMASK(4, 0)
299 #define BE_TXD_INFO5_NDPA_DURATION GENMASK(31, 16)
302 #define BE_TXD_INFO6_UL_APEP_LEN GENMASK(11, 0)
307 #define BE_TXD_INFO6_UL_RF_GAIN_IDX GENMASK(31, 22)
310 #define BE_TXD_INFO7_UL_FIXED_GAIN_EN BIT(0)
321 #define BE_TXD_INFO7_EXTEND_MODE_SEL GENMASK(31, 28)
324 #define AX_RXD_RPKT_LEN_MASK GENMASK(13, 0)
331 #define AX_RXD_LONG_RXD BIT(31)
334 #define AX_RXD_PPDU_TYPE_MASK GENMASK(3, 0)
345 #define AX_RXD_BW_MASK GENMASK(31, 30)
346 #define AX_RXD_BW_v1_MASK GENMASK(31, 29)
349 #define AX_RXD_FREERUN_CNT_MASK GENMASK(31, 0)
352 #define AX_RXD_A1_MATCH BIT(0)
374 #define AX_RXD_TYPE_MASK GENMASK(1, 0)
386 #define AX_RXD_FRAG_MASK GENMASK(31, 28)
389 #define AX_RXD_SEC_CAM_IDX_MASK GENMASK(7, 0)
398 #define AX_RXD_MAC_ADDR_MASK GENMASK(31, 0)
401 #define AX_RXD_MAC_ADDR_H_MASK GENMASK(15, 0)
413 #define RTW89_RXINFO_USER_MAC_ID_VALID BIT(0)
426 #define RTW89_RXINFO_W0_USR_NUM GENMASK(3, 0)
427 #define RTW89_RXINFO_W0_USR_NUM_V1 GENMASK(4, 0)
434 #define RTW89_RXINFO_W0_LONG_RXD GENMASK(31, 30)
435 #define RTW89_RXINFO_W1_SERVICE GENMASK(15, 0)
443 #define RTW89_PHY_STS_HDR_W0_IE_MAP GENMASK(4, 0)
447 #define RTW89_PHY_STS_HDR_W0_RSSI_AVG GENMASK(31, 24)
448 #define RTW89_PHY_STS_HDR_W1_RSSI_A GENMASK(7, 0)
451 #define RTW89_PHY_STS_HDR_W1_RSSI_D GENMASK(31, 24)
464 #define RTW89_PHY_STS_IEHDR_TYPE GENMASK(4, 0)
468 #define BE_RXD_RPKT_LEN_MASK GENMASK(13, 0)
475 #define BE_RXD_LONG_RXD BIT(31)
478 #define BE_RXD_PKT_ID_MASK GENMASK(11, 0)
484 #define BE_RXD_MAC_ID_MASK GENMASK(7, 0)
491 #define BE_RXD_TID_MASK GENMASK(31, 28)
494 #define BE_RXD_SEC_TYPE_MASK GENMASK(3, 0)
516 #define BE_RXD_GET_CH_INFO_V1_MASK GENMASK(31, 30)
519 #define BE_RXD_PPDU_TYPE_MASK GENMASK(7, 0)
524 #define BE_RXD_RX_DATARATE_MASK GENMASK(31, 20)
527 #define BE_RXD_FREERUN_CNT_MASK GENMASK(31, 0)
530 #define BE_RXD_ADDR_CAM_MASK GENMASK(7, 0)
537 #define BE_RXD_SEC_CAM_IDX_MASK GENMASK(31, 24)
540 #define BE_RXD_PATTERN_IDX_MASK GENMASK(4, 0)
556 #define BE_RXD_MAC_ADDR_MASK GENMASK(31, 0)
559 #define BE_RXD_MAC_ADDR_H_MASK GENMASK(15, 0)
583 #define RTW89_PHY_STS_IE00_V2_W4_RPL_TD_A GENMASK(8, 0)
586 #define RTW89_PHY_STS_IE00_V2_W5_RPL_TD_D GENMASK(8, 0)
599 #define RTW89_PHY_STS_IE01_W0_RX_PATH_EN GENMASK(31, 28)
601 #define RTW89_PHY_STS_IE01_W1_PREMB_CFO GENMASK(31, 20)
602 #define RTW89_PHY_STS_IE01_W2_AVG_SNR GENMASK(5, 0)
621 #define RTW89_PHY_STS_IE01_V2_W5_BW_IDX GENMASK(31, 29)
628 	RTW89_TXCH_ACH0	= 0,
636 	RTW89_TXCH_CH8	= 8,  /* MGMT Band 0 */
637 	RTW89_TXCH_CH9	= 9,  /* HI Band 0 */
644 	RTW89_TXCH_MAX = RTW89_TXCH_NUM - 1
648 	RTW89_RXCH_RXQ	= 0,
653 	RTW89_RXCH_MAX = RTW89_RXCH_NUM - 1
657 	RTW89_TX_QSEL_BE_0		= 0x00,
658 	RTW89_TX_QSEL_BK_0		= 0x01,
659 	RTW89_TX_QSEL_VI_0		= 0x02,
660 	RTW89_TX_QSEL_VO_0		= 0x03,
661 	RTW89_TX_QSEL_BE_1		= 0x04,
662 	RTW89_TX_QSEL_BK_1		= 0x05,
663 	RTW89_TX_QSEL_VI_1		= 0x06,
664 	RTW89_TX_QSEL_VO_1		= 0x07,
665 	RTW89_TX_QSEL_BE_2		= 0x08,
666 	RTW89_TX_QSEL_BK_2		= 0x09,
667 	RTW89_TX_QSEL_VI_2		= 0x0a,
668 	RTW89_TX_QSEL_VO_2		= 0x0b,
669 	RTW89_TX_QSEL_BE_3		= 0x0c,
670 	RTW89_TX_QSEL_BK_3		= 0x0d,
671 	RTW89_TX_QSEL_VI_3		= 0x0e,
672 	RTW89_TX_QSEL_VO_3		= 0x0f,
673 	RTW89_TX_QSEL_B0_BCN		= 0x10,
674 	RTW89_TX_QSEL_B0_HI		= 0x11,
675 	RTW89_TX_QSEL_B0_MGMT		= 0x12,
676 	RTW89_TX_QSEL_B0_NOPS		= 0x13,
677 	RTW89_TX_QSEL_B0_MGMT_FAST	= 0x14,
681 	RTW89_TX_QSEL_B1_BCN		= 0x18,
682 	RTW89_TX_QSEL_B1_HI		= 0x19,
683 	RTW89_TX_QSEL_B1_MGMT		= 0x1a,
684 	RTW89_TX_QSEL_B1_NOPS		= 0x1b,
685 	RTW89_TX_QSEL_B1_MGMT_FAST	= 0x1c,
697 	case 0:  in rtw89_core_get_qsel()
748 	case 0:  in rtw89_core_get_tid_indicate()
752 		return 0;  in rtw89_core_get_tid_indicate()