Lines Matching +full:0 +full:- +full:31
1 /* SPDX-License-Identifier: ISC */
10 #define MT_RXD0_LENGTH GENMASK(15, 0)
12 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
22 #define MT_RXD1_NORMAL_BSSID GENMASK(31, 26)
24 #define MT_RXD1_FIRST_AMSDU_FRAME GENMASK(1, 0)
26 #define MT_RXD1_LAST_AMSDU_FRAME BIT(0)
39 #define MT_RXD1_NORMAL_HTC_VLD BIT(0)
41 #define MT_RXD2_NORMAL_NON_AMPDU BIT(31)
59 #define MT_RXD2_NORMAL_WLAN_IDX GENMASK(7, 0)
61 #define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)
70 #define MT_RXD3_NORMAL_RXV_SEQ GENMASK(7, 0)
72 #define MT_RXD4_FRAME_CONTROL GENMASK(15, 0)
74 #define MT_RXD6_SEQ_CTRL GENMASK(15, 0)
75 #define MT_RXD6_QOS_CTL GENMASK(31, 16)
77 #define MT_RXD7_HT_CONTROL GENMASK(31, 0)
79 #define MT_RXV1_ACID_DET_H BIT(31)
93 #define MT_RXV1_TX_RATE GENMASK(6, 0)
95 #define MT_RXV2_SEL_ANT BIT(31)
99 #define MT_RXV2_LENGTH GENMASK(20, 0)
101 #define MT_RXV3_WB_RSSI GENMASK(31, 24)
104 #define MT_RXV4_RCPI3 GENMASK(31, 24)
107 #define MT_RXV4_RCPI0 GENMASK(7, 0)
109 #define MT_RXV5_FOE GENMASK(11, 0)
111 #define MT_RXV6_NF3 GENMASK(31, 24)
114 #define MT_RXV6_NF0 GENMASK(7, 0)
136 MT_TX_MCU_PORT_RX_Q0 = 0,
140 MT_TX_MCU_PORT_RX_FWDL = 0x1e
150 #define MT_CT_INFO_APPLY_TXD BIT(0)
156 #define MT_TXD0_P_IDX BIT(31)
161 #define MT_TXD0_TX_BYTES GENMASK(15, 0)
163 #define MT_TXD1_OWN_MAC GENMASK(31, 26)
173 #define MT_TXD1_WLAN_IDX GENMASK(7, 0)
175 #define MT_TXD2_FIX_RATE BIT(31)
190 #define MT_TXD2_SUB_TYPE GENMASK(3, 0)
192 #define MT_TXD3_SN_VALID BIT(31)
198 #define MT_TXD3_NO_ACK BIT(0)
200 #define MT_TXD4_PN_LOW GENMASK(31, 0)
202 #define MT_TXD5_PN_HIGH GENMASK(31, 16)
208 #define MT_TXD5_PID GENMASK(7, 0)
210 #define MT_TXD6_FIXED_RATE BIT(31)
218 #define MT_TXD6_BW GENMASK(1, 0)
220 /* MT7663 DW7 HW-AMSDU */
228 #define MT_TXD8_L_SUB_TYPE GENMASK(3, 0)
233 #define MT_TX_RATE_IDX GENMASK(5, 0)
235 #define MT_TX_FREE_MSDU_ID_CNT GENMASK(6, 0)
237 #define MT_TXS0_PID GENMASK(31, 24)
252 #define MT_TXS0_TX_RATE GENMASK(11, 0)
254 #define MT_TXS1_ANT_ID GENMASK(31, 20)
262 #define MT_TXS1_TX_POWER_DBM GENMASK(6, 0)
264 #define MT_TXS2_WCID GENMASK(31, 24)
266 #define MT_TXS2_TX_DELAY GENMASK(15, 0)
268 #define MT_TXS3_LAST_TX_RATE GENMASK(31, 29)
271 #define MT_TXS3_F1_TSSI0 GENMASK(11, 0)
272 #define MT_TXS3_F0_SEQNO GENMASK(11, 0)
274 #define MT_TXS4_F0_TIMESTAMP GENMASK(31, 0)
276 #define MT_TXS4_F1_TSSI2 GENMASK(11, 0)
278 #define MT_TXS5_F0_FRONT_TIME GENMASK(24, 0)
281 #define MT_TXS5_F1_NOISE_0 GENMASK(7, 0)
283 #define MT_TXS6_F1_RCPI_3 GENMASK(31, 24)
286 #define MT_TXS6_F1_RCPI_0 GENMASK(7, 0)