ipa/reg/ipa_reg-v3.5.1.c

1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
13 	[COMP_CFG_ENABLE]				= BIT(0),
18 						/* Bits 5-31 reserved */
21 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
24 	[CLKON_RX]					= BIT(0),
46 						/* Bits 22-31 reserved */
49 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
52 	[ROUTE_DIS]					= BIT(0),
57 						/* Bits 22-23 reserved */
59 						/* Bits 25-31 reserved */
62 REG_FIELDS(ROUTE, route, 0x00000048);
65 	[MEM_SIZE]					= GENMASK(15, 0),
66 	[MEM_BADDR]					= GENMASK(31, 16),
69 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
72 	[GEN_QMB_0_MAX_WRITES]				= GENMASK(3, 0),
74 						/* Bits 8-31 reserved */
77 REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
80 	[GEN_QMB_0_MAX_READS]				= GENMASK(3, 0),
84 REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);
87 	[IPV6_ROUTER_HASH]				= BIT(0),
88 						/* Bits 1-3 reserved */
90 						/* Bits 5-7 reserved */
92 						/* Bits 9-11 reserved */
94 						/* Bits 13-31 reserved */
97 REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x0000090);
99 /* Valid bits defined by ipa->available */
100 REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x0000010c, 0x0004);
102 REG(IPA_BCR, ipa_bcr, 0x000001d0);
105 	[IPA_BASE_ADDR]					= GENMASK(16, 0),
106 						/* Bits 17-31 reserved */
110 REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
112 /* Valid bits defined by ipa->available */
113 REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
116 						/* Bits 0-3 reserved */
118 						/* Bits 5-31 reserved */
121 REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0);
124 	[TX0_PREFETCH_DISABLE]				= BIT(0),
127 						/* Bits 5-31 reserved */
130 REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
133 	[MAX_PIPES]					= GENMASK(3, 0),
134 						/* Bits 4-7 reserved */
136 						/* Bits 13-15 reserved */
138 						/* Bits 21-23 reserved */
140 						/* Bits 28-31 reserved */
143 REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210);
146 	[ENTER_IDLE_DEBOUNCE_THRESH]			= GENMASK(15, 0),
148 						/* Bits 17-31 reserved */
151 REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000220);
154 	[X_MIN_LIM]					= GENMASK(5, 0),
155 						/* Bits 6-7 reserved */
157 						/* Bits 14-15 reserved */
159 						/* Bits 22-23 reserved */
161 						/* Bits 30-31 reserved */
165 		  0x00000400, 0x0020);
168 	[X_MIN_LIM]					= GENMASK(5, 0),
169 						/* Bits 6-7 reserved */
171 						/* Bits 14-15 reserved */
173 						/* Bits 22-23 reserved */
175 						/* Bits 30-31 reserved */
179 		  0x00000404, 0x0020);
182 	[X_MIN_LIM]					= GENMASK(5, 0),
183 						/* Bits 6-7 reserved */
185 						/* Bits 14-15 reserved */
187 						/* Bits 22-23 reserved */
189 						/* Bits 30-31 reserved */
193 		  0x00000500, 0x0020);
196 	[X_MIN_LIM]					= GENMASK(5, 0),
197 						/* Bits 6-7 reserved */
199 						/* Bits 14-15 reserved */
201 						/* Bits 22-23 reserved */
203 						/* Bits 30-31 reserved */
207 		  0x00000504, 0x0020);
210 	[ENDP_SUSPEND]					= BIT(0),
212 						/* Bits 2-31 reserved */
215 REG_STRIDE_FIELDS(ENDP_INIT_CTRL, endp_init_ctrl, 0x00000800, 0x0070);
218 	[FRAG_OFFLOAD_EN]				= BIT(0),
223 						/* Bits 9-31 reserved */
226 REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
229 	[NAT_EN]					= GENMASK(1, 0),
230 						/* Bits 2-31 reserved */
233 REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
236 	[HDR_LEN]					= GENMASK(5, 0),
245 						/* Bits 29-31 reserved */
248 REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
251 	[HDR_ENDIANNESS]				= BIT(0),
257 						/* Bits 14-31 reserved */
260 REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
263 	   0x00000818, 0x0070);
266 	[ENDP_MODE]					= GENMASK(2, 0),
269 						/* Bits 9-11 reserved */
274 						/* Bit 31 reserved */
277 REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070);
280 	[AGGR_EN]					= GENMASK(1, 0),
289 						/* Bits 25-31 reserved */
292 REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070);
295 	[HOL_BLOCK_EN]					= BIT(0),
296 						/* Bits 1-31 reserved */
300 		  0x0000082c, 0x0070);
304 	[TIMER_BASE_VALUE]				= GENMASK(31, 0),
308 		  0x00000830, 0x0070);
311 	[DEAGGR_HDR_LEN]				= GENMASK(5, 0),
317 	[MAX_PACKET_LEN]				= GENMASK(31, 16),
320 REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070);
323 	[ENDP_RSRC_GRP]					= GENMASK(1, 0),
324 						/* Bits 2-31 reserved */
327 REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070);
330 	[SEQ_TYPE]					= GENMASK(7, 0),
332 						/* Bits 16-31 reserved */
335 REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070);
338 	[STATUS_EN]					= BIT(0),
340 						/* Bits 6-7 reserved */
342 						/* Bits 9-31 reserved */
345 REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070);
348 	[FILTER_HASH_MSK_SRC_ID]			= BIT(0),
355 	[FILTER_HASH_MSK_ALL]				= GENMASK(6, 0),
356 						/* Bits 7-15 reserved */
365 						/* Bits 23-31 reserved */
369 		  0x0000085c, 0x0070);
372 REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP);
375 REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP);
378 REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP);
381 	[UC_INTR]					= BIT(0),
382 						/* Bits 1-31 reserved */
385 REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP);
387 /* Valid bits defined by ipa->available */
389 	   0x00003030 + 0x1000 * GSI_EE_AP, 0x0004);
391 /* Valid bits defined by ipa->available */
393 	   0x00003034 + 0x1000 * GSI_EE_AP, 0x0004);
395 /* Valid bits defined by ipa->available */
397 	   0x00003038 + 0x1000 * GSI_EE_AP, 0x0004);