1 // SPDX-License-Identifier: GPL-2.0 2 3 /* Copyright (C) 2022-2024 Linaro Ltd. */ 4 5 #include <linux/array_size.h> 6 #include <linux/bits.h> 7 #include <linux/types.h> 8 9 #include "../ipa_reg.h" 10 #include "../ipa_version.h" 11 12 static const u32 reg_comp_cfg_fmask[] = { 13 [COMP_CFG_ENABLE] = BIT(0), 14 [GSI_SNOC_BYPASS_DIS] = BIT(1), 15 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2), 16 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3), 17 [IPA_DCMP_FAST_CLK_EN] = BIT(4), 18 /* Bits 5-31 reserved */ 19 }; 20 21 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c); 22 23 static const u32 reg_clkon_cfg_fmask[] = { 24 [CLKON_RX] = BIT(0), 25 [CLKON_PROC] = BIT(1), 26 [TX_WRAPPER] = BIT(2), 27 [CLKON_MISC] = BIT(3), 28 [RAM_ARB] = BIT(4), 29 [FTCH_HPS] = BIT(5), 30 [FTCH_DPS] = BIT(6), 31 [CLKON_HPS] = BIT(7), 32 [CLKON_DPS] = BIT(8), 33 [RX_HPS_CMDQS] = BIT(9), 34 [HPS_DPS_CMDQS] = BIT(10), 35 [DPS_TX_CMDQS] = BIT(11), 36 [RSRC_MNGR] = BIT(12), 37 [CTX_HANDLER] = BIT(13), 38 [ACK_MNGR] = BIT(14), 39 [D_DCPH] = BIT(15), 40 [H_DCPH] = BIT(16), 41 /* Bit 17 reserved */ 42 [NTF_TX_CMDQS] = BIT(18), 43 [CLKON_TX_0] = BIT(19), 44 [CLKON_TX_1] = BIT(20), 45 [CLKON_FNR] = BIT(21), 46 /* Bits 22-31 reserved */ 47 }; 48 49 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044); 50 51 static const u32 reg_route_fmask[] = { 52 [ROUTE_DIS] = BIT(0), 53 [ROUTE_DEF_PIPE] = GENMASK(5, 1), 54 [ROUTE_DEF_HDR_TABLE] = BIT(6), 55 [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7), 56 [ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17), 57 /* Bits 22-23 reserved */ 58 [ROUTE_DEF_RETAIN_HDR] = BIT(24), 59 /* Bits 25-31 reserved */ 60 }; 61 62 REG_FIELDS(ROUTE, route, 0x00000048); 63 64 static const u32 reg_shared_mem_size_fmask[] = { 65 [MEM_SIZE] = GENMASK(15, 0), 66 [MEM_BADDR] = GENMASK(31, 16), 67 }; 68 69 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054); 70 71 static const u32 reg_qsb_max_writes_fmask[] = { 72 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0), 73 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4), 74 /* Bits 8-31 reserved */ 75 }; 76 77 REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074); 78 79 static const u32 reg_qsb_max_reads_fmask[] = { 80 [GEN_QMB_0_MAX_READS] = GENMASK(3, 0), 81 [GEN_QMB_1_MAX_READS] = GENMASK(7, 4), 82 }; 83 84 REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078); 85 86 static const u32 reg_filt_rout_hash_flush_fmask[] = { 87 [IPV6_ROUTER_HASH] = BIT(0), 88 /* Bits 1-3 reserved */ 89 [IPV6_FILTER_HASH] = BIT(4), 90 /* Bits 5-7 reserved */ 91 [IPV4_ROUTER_HASH] = BIT(8), 92 /* Bits 9-11 reserved */ 93 [IPV4_FILTER_HASH] = BIT(12), 94 /* Bits 13-31 reserved */ 95 }; 96 97 REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x0000090); 98 99 /* Valid bits defined by ipa->available */ 100 REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x0000010c, 0x0004); 101 102 REG(IPA_BCR, ipa_bcr, 0x000001d0); 103 104 static const u32 reg_local_pkt_proc_cntxt_fmask[] = { 105 [IPA_BASE_ADDR] = GENMASK(16, 0), 106 /* Bits 17-31 reserved */ 107 }; 108 109 /* Offset must be a multiple of 8 */ 110 REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8); 111 112 /* Valid bits defined by ipa->available */ 113 REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004); 114 115 static const u32 reg_counter_cfg_fmask[] = { 116 /* Bits 0-3 reserved */ 117 [AGGR_GRANULARITY] = GENMASK(8, 4), 118 /* Bits 5-31 reserved */ 119 }; 120 121 REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0); 122 123 static const u32 reg_ipa_tx_cfg_fmask[] = { 124 [TX0_PREFETCH_DISABLE] = BIT(0), 125 [TX1_PREFETCH_DISABLE] = BIT(1), 126 [PREFETCH_ALMOST_EMPTY_SIZE] = GENMASK(4, 2), 127 /* Bits 5-31 reserved */ 128 }; 129 130 REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc); 131 132 static const u32 reg_flavor_0_fmask[] = { 133 [MAX_PIPES] = GENMASK(3, 0), 134 /* Bits 4-7 reserved */ 135 [MAX_CONS_PIPES] = GENMASK(12, 8), 136 /* Bits 13-15 reserved */ 137 [MAX_PROD_PIPES] = GENMASK(20, 16), 138 /* Bits 21-23 reserved */ 139 [PROD_LOWEST] = GENMASK(27, 24), 140 /* Bits 28-31 reserved */ 141 }; 142 143 REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210); 144 145 static const u32 reg_idle_indication_cfg_fmask[] = { 146 [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0), 147 [CONST_NON_IDLE_ENABLE] = BIT(16), 148 /* Bits 17-31 reserved */ 149 }; 150 151 REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000220); 152 153 static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = { 154 [X_MIN_LIM] = GENMASK(5, 0), 155 /* Bits 6-7 reserved */ 156 [X_MAX_LIM] = GENMASK(13, 8), 157 /* Bits 14-15 reserved */ 158 [Y_MIN_LIM] = GENMASK(21, 16), 159 /* Bits 22-23 reserved */ 160 [Y_MAX_LIM] = GENMASK(29, 24), 161 /* Bits 30-31 reserved */ 162 }; 163 164 REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, 165 0x00000400, 0x0020); 166 167 static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = { 168 [X_MIN_LIM] = GENMASK(5, 0), 169 /* Bits 6-7 reserved */ 170 [X_MAX_LIM] = GENMASK(13, 8), 171 /* Bits 14-15 reserved */ 172 [Y_MIN_LIM] = GENMASK(21, 16), 173 /* Bits 22-23 reserved */ 174 [Y_MAX_LIM] = GENMASK(29, 24), 175 /* Bits 30-31 reserved */ 176 }; 177 178 REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, 179 0x00000404, 0x0020); 180 181 static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { 182 [X_MIN_LIM] = GENMASK(5, 0), 183 /* Bits 6-7 reserved */ 184 [X_MAX_LIM] = GENMASK(13, 8), 185 /* Bits 14-15 reserved */ 186 [Y_MIN_LIM] = GENMASK(21, 16), 187 /* Bits 22-23 reserved */ 188 [Y_MAX_LIM] = GENMASK(29, 24), 189 /* Bits 30-31 reserved */ 190 }; 191 192 REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, 193 0x00000500, 0x0020); 194 195 static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { 196 [X_MIN_LIM] = GENMASK(5, 0), 197 /* Bits 6-7 reserved */ 198 [X_MAX_LIM] = GENMASK(13, 8), 199 /* Bits 14-15 reserved */ 200 [Y_MIN_LIM] = GENMASK(21, 16), 201 /* Bits 22-23 reserved */ 202 [Y_MAX_LIM] = GENMASK(29, 24), 203 /* Bits 30-31 reserved */ 204 }; 205 206 REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, 207 0x00000504, 0x0020); 208 209 static const u32 reg_endp_init_ctrl_fmask[] = { 210 [ENDP_SUSPEND] = BIT(0), 211 [ENDP_DELAY] = BIT(1), 212 /* Bits 2-31 reserved */ 213 }; 214 215 REG_STRIDE_FIELDS(ENDP_INIT_CTRL, endp_init_ctrl, 0x00000800, 0x0070); 216 217 static const u32 reg_endp_init_cfg_fmask[] = { 218 [FRAG_OFFLOAD_EN] = BIT(0), 219 [CS_OFFLOAD_EN] = GENMASK(2, 1), 220 [CS_METADATA_HDR_OFFSET] = GENMASK(6, 3), 221 /* Bit 7 reserved */ 222 [CS_GEN_QMB_MASTER_SEL] = BIT(8), 223 /* Bits 9-31 reserved */ 224 }; 225 226 REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070); 227 228 static const u32 reg_endp_init_nat_fmask[] = { 229 [NAT_EN] = GENMASK(1, 0), 230 /* Bits 2-31 reserved */ 231 }; 232 233 REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070); 234 235 static const u32 reg_endp_init_hdr_fmask[] = { 236 [HDR_LEN] = GENMASK(5, 0), 237 [HDR_OFST_METADATA_VALID] = BIT(6), 238 [HDR_OFST_METADATA] = GENMASK(12, 7), 239 [HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13), 240 [HDR_OFST_PKT_SIZE_VALID] = BIT(19), 241 [HDR_OFST_PKT_SIZE] = GENMASK(25, 20), 242 [HDR_A5_MUX] = BIT(26), 243 [HDR_LEN_INC_DEAGG_HDR] = BIT(27), 244 [HDR_METADATA_REG_VALID] = BIT(28), 245 /* Bits 29-31 reserved */ 246 }; 247 248 REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070); 249 250 static const u32 reg_endp_init_hdr_ext_fmask[] = { 251 [HDR_ENDIANNESS] = BIT(0), 252 [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1), 253 [HDR_TOTAL_LEN_OR_PAD] = BIT(2), 254 [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3), 255 [HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4), 256 [HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10), 257 /* Bits 14-31 reserved */ 258 }; 259 260 REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070); 261 262 REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask, 263 0x00000818, 0x0070); 264 265 static const u32 reg_endp_init_mode_fmask[] = { 266 [ENDP_MODE] = GENMASK(2, 0), 267 /* Bit 3 reserved */ 268 [DEST_PIPE_INDEX] = GENMASK(8, 4), 269 /* Bits 9-11 reserved */ 270 [BYTE_THRESHOLD] = GENMASK(27, 12), 271 [PIPE_REPLICATION_EN] = BIT(28), 272 [PAD_EN] = BIT(29), 273 [HDR_FTCH_DISABLE] = BIT(30), 274 /* Bit 31 reserved */ 275 }; 276 277 REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070); 278 279 static const u32 reg_endp_init_aggr_fmask[] = { 280 [AGGR_EN] = GENMASK(1, 0), 281 [AGGR_TYPE] = GENMASK(4, 2), 282 [BYTE_LIMIT] = GENMASK(9, 5), 283 [TIME_LIMIT] = GENMASK(14, 10), 284 [PKT_LIMIT] = GENMASK(20, 15), 285 [SW_EOF_ACTIVE] = BIT(21), 286 [FORCE_CLOSE] = BIT(22), 287 /* Bit 23 reserved */ 288 [HARD_BYTE_LIMIT_EN] = BIT(24), 289 /* Bits 25-31 reserved */ 290 }; 291 292 REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070); 293 294 static const u32 reg_endp_init_hol_block_en_fmask[] = { 295 [HOL_BLOCK_EN] = BIT(0), 296 /* Bits 1-31 reserved */ 297 }; 298 299 REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en, 300 0x0000082c, 0x0070); 301 302 /* Entire register is a tick count */ 303 static const u32 reg_endp_init_hol_block_timer_fmask[] = { 304 [TIMER_BASE_VALUE] = GENMASK(31, 0), 305 }; 306 307 REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer, 308 0x00000830, 0x0070); 309 310 static const u32 reg_endp_init_deaggr_fmask[] = { 311 [DEAGGR_HDR_LEN] = GENMASK(5, 0), 312 [SYSPIPE_ERR_DETECTION] = BIT(6), 313 [PACKET_OFFSET_VALID] = BIT(7), 314 [PACKET_OFFSET_LOCATION] = GENMASK(13, 8), 315 [IGNORE_MIN_PKT_ERR] = BIT(14), 316 /* Bit 15 reserved */ 317 [MAX_PACKET_LEN] = GENMASK(31, 16), 318 }; 319 320 REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070); 321 322 static const u32 reg_endp_init_rsrc_grp_fmask[] = { 323 [ENDP_RSRC_GRP] = GENMASK(1, 0), 324 /* Bits 2-31 reserved */ 325 }; 326 327 REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070); 328 329 static const u32 reg_endp_init_seq_fmask[] = { 330 [SEQ_TYPE] = GENMASK(7, 0), 331 [SEQ_REP_TYPE] = GENMASK(15, 8), 332 /* Bits 16-31 reserved */ 333 }; 334 335 REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070); 336 337 static const u32 reg_endp_status_fmask[] = { 338 [STATUS_EN] = BIT(0), 339 [STATUS_ENDP] = GENMASK(5, 1), 340 /* Bits 6-7 reserved */ 341 [STATUS_LOCATION] = BIT(8), 342 /* Bits 9-31 reserved */ 343 }; 344 345 REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070); 346 347 static const u32 reg_endp_filter_router_hsh_cfg_fmask[] = { 348 [FILTER_HASH_MSK_SRC_ID] = BIT(0), 349 [FILTER_HASH_MSK_SRC_IP] = BIT(1), 350 [FILTER_HASH_MSK_DST_IP] = BIT(2), 351 [FILTER_HASH_MSK_SRC_PORT] = BIT(3), 352 [FILTER_HASH_MSK_DST_PORT] = BIT(4), 353 [FILTER_HASH_MSK_PROTOCOL] = BIT(5), 354 [FILTER_HASH_MSK_METADATA] = BIT(6), 355 [FILTER_HASH_MSK_ALL] = GENMASK(6, 0), 356 /* Bits 7-15 reserved */ 357 [ROUTER_HASH_MSK_SRC_ID] = BIT(16), 358 [ROUTER_HASH_MSK_SRC_IP] = BIT(17), 359 [ROUTER_HASH_MSK_DST_IP] = BIT(18), 360 [ROUTER_HASH_MSK_SRC_PORT] = BIT(19), 361 [ROUTER_HASH_MSK_DST_PORT] = BIT(20), 362 [ROUTER_HASH_MSK_PROTOCOL] = BIT(21), 363 [ROUTER_HASH_MSK_METADATA] = BIT(22), 364 [ROUTER_HASH_MSK_ALL] = GENMASK(22, 16), 365 /* Bits 23-31 reserved */ 366 }; 367 368 REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg, 369 0x0000085c, 0x0070); 370 371 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 372 REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP); 373 374 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 375 REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP); 376 377 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 378 REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP); 379 380 static const u32 reg_ipa_irq_uc_fmask[] = { 381 [UC_INTR] = BIT(0), 382 /* Bits 1-31 reserved */ 383 }; 384 385 REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP); 386 387 /* Valid bits defined by ipa->available */ 388 REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info, 389 0x00003030 + 0x1000 * GSI_EE_AP, 0x0004); 390 391 /* Valid bits defined by ipa->available */ 392 REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en, 393 0x00003034 + 0x1000 * GSI_EE_AP, 0x0004); 394 395 /* Valid bits defined by ipa->available */ 396 REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr, 397 0x00003038 + 0x1000 * GSI_EE_AP, 0x0004); 398 399 static const struct reg *reg_array[] = { 400 [COMP_CFG] = ®_comp_cfg, 401 [CLKON_CFG] = ®_clkon_cfg, 402 [ROUTE] = ®_route, 403 [SHARED_MEM_SIZE] = ®_shared_mem_size, 404 [QSB_MAX_WRITES] = ®_qsb_max_writes, 405 [QSB_MAX_READS] = ®_qsb_max_reads, 406 [FILT_ROUT_HASH_FLUSH] = ®_filt_rout_hash_flush, 407 [STATE_AGGR_ACTIVE] = ®_state_aggr_active, 408 [IPA_BCR] = ®_ipa_bcr, 409 [LOCAL_PKT_PROC_CNTXT] = ®_local_pkt_proc_cntxt, 410 [AGGR_FORCE_CLOSE] = ®_aggr_force_close, 411 [COUNTER_CFG] = ®_counter_cfg, 412 [IPA_TX_CFG] = ®_ipa_tx_cfg, 413 [FLAVOR_0] = ®_flavor_0, 414 [IDLE_INDICATION_CFG] = ®_idle_indication_cfg, 415 [SRC_RSRC_GRP_01_RSRC_TYPE] = ®_src_rsrc_grp_01_rsrc_type, 416 [SRC_RSRC_GRP_23_RSRC_TYPE] = ®_src_rsrc_grp_23_rsrc_type, 417 [DST_RSRC_GRP_01_RSRC_TYPE] = ®_dst_rsrc_grp_01_rsrc_type, 418 [DST_RSRC_GRP_23_RSRC_TYPE] = ®_dst_rsrc_grp_23_rsrc_type, 419 [ENDP_INIT_CTRL] = ®_endp_init_ctrl, 420 [ENDP_INIT_CFG] = ®_endp_init_cfg, 421 [ENDP_INIT_NAT] = ®_endp_init_nat, 422 [ENDP_INIT_HDR] = ®_endp_init_hdr, 423 [ENDP_INIT_HDR_EXT] = ®_endp_init_hdr_ext, 424 [ENDP_INIT_HDR_METADATA_MASK] = ®_endp_init_hdr_metadata_mask, 425 [ENDP_INIT_MODE] = ®_endp_init_mode, 426 [ENDP_INIT_AGGR] = ®_endp_init_aggr, 427 [ENDP_INIT_HOL_BLOCK_EN] = ®_endp_init_hol_block_en, 428 [ENDP_INIT_HOL_BLOCK_TIMER] = ®_endp_init_hol_block_timer, 429 [ENDP_INIT_DEAGGR] = ®_endp_init_deaggr, 430 [ENDP_INIT_RSRC_GRP] = ®_endp_init_rsrc_grp, 431 [ENDP_INIT_SEQ] = ®_endp_init_seq, 432 [ENDP_STATUS] = ®_endp_status, 433 [ENDP_FILTER_ROUTER_HSH_CFG] = ®_endp_filter_router_hsh_cfg, 434 [IPA_IRQ_STTS] = ®_ipa_irq_stts, 435 [IPA_IRQ_EN] = ®_ipa_irq_en, 436 [IPA_IRQ_CLR] = ®_ipa_irq_clr, 437 [IPA_IRQ_UC] = ®_ipa_irq_uc, 438 [IRQ_SUSPEND_INFO] = ®_irq_suspend_info, 439 [IRQ_SUSPEND_EN] = ®_irq_suspend_en, 440 [IRQ_SUSPEND_CLR] = ®_irq_suspend_clr, 441 }; 442 443 const struct regs ipa_regs_v3_5_1 = { 444 .reg_count = ARRAY_SIZE(reg_array), 445 .reg = reg_array, 446 }; 447