amd/atl/reg_fields.h

1 /* SPDX-License-Identifier: GPL-2.0 */
50  *	D18F1x208 [System Fabric ID Mask 0]
51  *	DF3	ComponentIdMask	[9:0]
53  *	D18F1x150 [System Fabric ID Mask 0]
54  *	DF3p5	ComponentIdMask	[15:0]
56  *	D18F4x1B0 [System Fabric ID Mask 0]
57  *	DF4	ComponentIdMask	[15:0]
58  *	DF4p5	ComponentIdMask	[15:0]
60 #define DF3_COMPONENT_ID_MASK	GENMASK(9, 0)
61 #define DF4_COMPONENT_ID_MASK	GENMASK(15, 0)
72  *	DF2	DstFabricID	[7:0]
73  *	DF3	DstFabricID	[9:0]
74  *	DF3	DstFabricID	[11:0]
82 #define DF2_DST_FABRIC_ID	GENMASK(7, 0)
83 #define DF3_DST_FABRIC_ID	GENMASK(9, 0)
84 #define DF3p5_DST_FABRIC_ID	GENMASK(11, 0)
103  *	DF3p5	DieIdMask	[15:0]
106  *	DF4	DieIdMask	[15:0]
107  *	DF4p5	DieIdMask	[15:0]
111 #define DF4_DIE_ID_MASK		GENMASK(15, 0)
140  *	DF2	AddrRngVal	[0]
141  *	DF3	AddrRngVal	[0]
142  *	DF3p5	AddrRngVal	[0]
145  *	DF4	AddrRngVal	[0]
148  *	DF4p5	AddrRngVal	[0]
150 #define DF_ADDR_RANGE_VAL	BIT(0)
161  *	DF2	DramBaseAddr	[31:12]
162  *	DF3	DramBaseAddr	[31:12]
163  *	DF3p5	DramBaseAddr	[31:12]
166  *	DF4	DramBaseAddr	[27:0]
169  *	DF4p5	DramBaseAddr	[27:0]
171 #define DF2_BASE_ADDR		GENMASK(31, 12)
172 #define DF4_BASE_ADDR		GENMASK(27, 0)
183  *	DF2	DramHoleBase	[31:24]
184  *	DF3	DramHoleBase	[31:24]
185  *	DF3p5	DramHoleBase	[31:24]
188  *	DF4	DramHoleBase	[31:24]
189  *	DF4p5	DramHoleBase	[31:24]
191 #define DF_DRAM_HOLE_BASE_MASK	GENMASK(31, 24)
202  *	DF2	DramLimitAddr	[31:12]
203  *	DF3	DramLimitAddr	[31:12]
204  *	DF3p5	DramLimitAddr	[31:12]
207  *	DF4	DramLimitAddr	[27:0]
210  *	DF4p5	DramLimitAddr	[27:0]
212 #define DF2_DRAM_LIMIT_ADDR	GENMASK(31, 12)
213 #define DF4_DRAM_LIMIT_ADDR	GENMASK(27, 0)
264  *	DF2	HiAddrOffset	[31:20]
265  *	DF3	HiAddrOffset	[31:12]
266  *	DF3p5	HiAddrOffset	[31:12]
271  *	MI300	HiAddrOffset	[31:1]
273 #define DF2_HI_ADDR_OFFSET	GENMASK(31, 20)
274 #define DF3_HI_ADDR_OFFSET	GENMASK(31, 12)
277 #define DF4_HI_ADDR_OFFSET	GENMASK(31, 1)
288  *	DF2	HiAddrOffsetEn	[0]
289  *	DF3	HiAddrOffsetEn	[0]
290  *	DF3p5	HiAddrOffsetEn	[0]
293  *	DF4	HiAddrOffsetEn	[0]
294  *	DF4p5	HiAddrOffsetEn	[0]
296 #define DF_HI_ADDR_OFFSET_EN	BIT(0)
312  *	DF4	IntLvAddrSel	[2:0]
315  *	DF4p5	IntLvAddrSel	[2:0]
319 #define DF4_INTLV_ADDR_SEL	GENMASK(2, 0)
418  * Log2 Address 64K Space 0
427  *	D18F2x90 [Non-power-of-2 channel Configuration Register for COH_ST DRAM Address Maps]
428  *	DF3	Log2Addr64KSpace0	[5:0]
434 #define DF_LOG2_ADDR_64K_SPACE0		GENMASK(5, 0)
482  *	D18F1x208 [System Fabric ID Mask 0]
485  *	D18F1x150 [System Fabric ID Mask 0]
486  *	DF3p5	NodeIdMask	[31:16]
488  *	D18F4x1B0 [System Fabric ID Mask 0]
489  *	DF4	NodeIdMask	[31:16]
490  *	DF4p5	NodeIdMask	[31:16]
493 #define DF4_NODE_ID_MASK	GENMASK(31, 16)
506  *	DF3	NodeIdShift	[3:0]
509  *	DF3p5	NodeIdShift	[3:0]
512  *	DF4	NodeIdShift	[3:0]
513  *	DF4p5	NodeIdShift	[3:0]
515 #define DF3_NODE_ID_SHIFT	GENMASK(3, 0)
573  *	DF3p5	SocketIdMask	[31:16]
576  *	DF4	SocketIdMask	[31:16]
577  *	DF4p5	SocketIdMask	[31:16]
581 #define DF4_SOCKET_ID_MASK	GENMASK(31, 16)
592  *	DF2	SocketIdShift	[31:28]
604 #define DF2_SOCKET_ID_SHIFT	GENMASK(31, 28)