Lines Matching +full:0 +full:- +full:31
1 /* SPDX-License-Identifier: ISC */
9 MT_HIF0 = 0x0,
11 MT_LMAC_AC00 = 0x0,
15 MT_LMAC_ALTX0 = 0x10,
24 #define MT_RXD0_LENGTH GENMASK(15, 0)
26 #define MT_RXD0_PKT_TYPE GENMASK(31, 27)
32 #define MT_RXD0_SW_PKT_TYPE_MASK GENMASK(31, 16)
33 #define MT_RXD0_SW_PKT_TYPE_MAP 0x380F
34 #define MT_RXD0_SW_PKT_TYPE_FRAME 0x3801
37 #define MT_RXD1_NORMAL_WLAN_IDX GENMASK(11, 0)
51 #define MT_RXD1_NORMAL_SEC_DONE BIT(31)
54 #define MT_RXD2_NORMAL_BSSID GENMASK(5, 0)
69 #define MT_RXD2_NORMAL_BF_REPORT BIT(31)
72 #define MT_RXD3_NORMAL_RXV_SEQ GENMASK(7, 0)
75 #define MT_RXD3_NORMAL_U2M BIT(0)
83 #define MT_RXD3_NORMAL_VLAN2ETH BIT(31)
86 #define MT_RXD4_NORMAL_PAYLOAD_FORMAT GENMASK(1, 0)
87 #define MT_RXD4_FIRST_AMSDU_FRAME GENMASK(1, 0)
89 #define MT_RXD4_LAST_AMSDU_FRAME BIT(0)
94 #define MT_RXD8_FRAME_CONTROL GENMASK(15, 0)
96 #define MT_RXD10_SEQ_CTRL GENMASK(15, 0)
97 #define MT_RXD10_QOS_CTL GENMASK(31, 16)
99 #define MT_RXD11_HT_CONTROL GENMASK(31, 0)
101 /* P-RXV */
102 #define MT_PRXV_TX_RATE GENMASK(6, 0)
109 #define MT_PRXV_RCPI3 GENMASK(31, 24)
112 #define MT_PRXV_RCPI0 GENMASK(7, 0)
116 #define MT_PRXV_FRAME_MODE GENMASK(2, 0)
119 /* C-RXV */
130 #define MT_CRXV_HE_DOPPLER BIT(0)
139 #define MT_CRXV_HE_RU0 GENMASK(8, 0)
142 #define MT_CRXV_HE_RU3_L GENMASK(31, 27)
143 #define MT_CRXV_HE_RU3_H GENMASK(3, 0)
152 #define MT_CRXV_EHT_DOPPLER BIT(0)
159 #define MT_CRXV_EHT_RU0 GENMASK(8, 0)
162 #define MT_CRXV_EHT_RU3_L GENMASK(31, 27)
163 #define MT_CRXV_EHT_RU3_H GENMASK(3, 0)
187 MT_TX_MCU_PORT_RX_Q0 = 0x20,
191 MT_TX_MCU_PORT_RX_FWDL = 0x3e
207 #define MT_CT_INFO_APPLY_TXD BIT(0)
216 #define MT_TXD0_Q_IDX GENMASK(31, 25)
219 #define MT_TXD0_TX_BYTES GENMASK(15, 0)
221 #define MT_TXD1_FIXED_RATE BIT(31)
229 #define MT_TXD1_WLAN_IDX GENMASK(11, 0)
231 #define MT_TXD2_POWER_OFFSET GENMASK(31, 26)
241 #define MT_TXD2_SUB_TYPE GENMASK(3, 0)
243 #define MT_TXD3_SN_VALID BIT(31)
255 #define MT_TXD3_NO_ACK BIT(0)
257 #define MT_TXD4_PN_LOW GENMASK(31, 0)
259 #define MT_TXD5_PN_HIGH GENMASK(31, 16)
267 #define MT_TXD5_PID GENMASK(7, 0)
269 #define MT_TXD6_TX_SRC GENMASK(31, 30)
282 #define MT_TXD7_TXD_LEN GENMASK(31, 30)
289 #define MT_TXD7_TX_TIME GENMASK(9, 0)
293 #define MT_TXP_BUF_LEN GENMASK(11, 0)
301 /* VHT/HE only use bits 0-3 */
302 #define MT_TX_RATE_IDX GENMASK(5, 0)
304 #define MT_TXFREE0_PKT_TYPE GENMASK(31, 27)
306 #define MT_TXFREE0_RX_BYTE GENMASK(15, 0)
310 #define MT_TXFREE_INFO_PAIR BIT(31)
313 #define MT_TXFREE_INFO_MSDU_ID GENMASK(14, 0)
317 #define MT_TXS0_BW GENMASK(31, 29)
333 #define MT_TXS0_TX_RATE GENMASK(13, 0)
335 #define MT_TXS1_SEQNO GENMASK(31, 20)
338 #define MT_TXS1_TX_POWER_DBM GENMASK(7, 0)
340 #define MT_TXS2_BF_STATUS GENMASK(31, 30)
343 #define MT_TXS2_TX_DELAY GENMASK(15, 0)
345 #define MT_TXS3_PID GENMASK(31, 24)
350 #define MT_TXS3_LAST_TX_RATE GENMASK(2, 0)
352 #define MT_TXS4_TIMESTAMP GENMASK(31, 0)
355 #define MT_TXS5_F0_FINAL_MPDU BIT(31)
358 #define MT_TXS5_F0_FRONT_TIME GENMASK(24, 0)
359 #define MT_TXS5_F1_MPDU_TX_COUNT GENMASK(31, 24)
360 #define MT_TXS5_F1_MPDU_TX_BYTES GENMASK(23, 0)
362 #define MT_TXS6_F0_NOISE_3 GENMASK(31, 24)
365 #define MT_TXS6_F0_NOISE_0 GENMASK(7, 0)
366 #define MT_TXS6_F1_MPDU_FAIL_COUNT GENMASK(31, 24)
367 #define MT_TXS6_F1_MPDU_FAIL_BYTES GENMASK(23, 0)
369 #define MT_TXS7_F0_RCPI_3 GENMASK(31, 24)
372 #define MT_TXS7_F0_RCPI_0 GENMASK(7, 0)
373 #define MT_TXS7_F1_MPDU_RETRY_COUNT GENMASK(31, 24)
374 #define MT_TXS7_F1_MPDU_RETRY_BYTES GENMASK(23, 0)
379 #define MT_TXS5_MPDU_TX_BYTE GENMASK(14, 0)
383 #define MT_TXS6_MPDU_FAIL_BYTE GENMASK(14, 0)
387 #define MT_TXS7_MPDU_RETRY_BYTE GENMASK(14, 0)