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/linux-6.12.1/include/linux/
Ddmaengine.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
18 * typedef dma_cookie_t - an opaque DMA cookie
20 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
31 * enum dma_status - DMA transaction status
46 * enum dma_transaction_type - DMA transaction types/indexes
49 * automatically set as dma devices are registered.
68 /* last transaction type for creation of the capabilities mask */
73 * enum dma_transfer_direction - dma transfer mode and direction indicator
89 * ----------------------------
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/linux-6.12.1/sound/pci/
Dad1889.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2004, Kyle McMartin <kyle@parisc-linux.org>
9 #define AD_DS_WSMC 0x00 /* wave/synthesis channel mixer control */
10 #define AD_DS_WSMC_SYEN 0x0004 /* synthesis channel enable */
12 #define AD_DS_WSMC_WA16 0x0100 /* wave channel 16bit select */
13 #define AD_DS_WSMC_WAST 0x0200 /* wave channel stereo select */
14 #define AD_DS_WSMC_WAEN 0x0400 /* wave channel enable */
17 #define AD_DS_RAMC 0x02 /* resampler/ADC channel mixer control */
18 #define AD_DS_RAMC_AD16 0x0001 /* ADC channel 16bit select */
19 #define AD_DS_RAMC_ADST 0x0002 /* ADC channel stereo select */
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/linux-6.12.1/arch/parisc/include/asm/
Ddma.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* asm/dma.h: Defines for using and allocating dma channels.
4 * High DMA channel support & info by Hannu Savolainen
20 ** DMA_CHUNK_SIZE is used by the SCSI mid-layer to break up
28 /* The maximum address that we can perform a DMA transfer to on this platform
29 ** New dynamic DMA interfaces should obsolete this....
34 ** We don't have DMA channels... well V-class does but the
35 ** Dynamic DMA Mapping interface will support them... right? :^)
36 ** Note: this is not relevant right now for PA-RISC, but we cannot
38 ** won't compile :-(
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/linux-6.12.1/drivers/video/fbdev/
Dpxa3xx-regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
20 #define FBR0 (0x020) /* DMA Channel 0 Frame Branch Register */
21 #define FBR1 (0x024) /* DMA Channel 1 Frame Branch Register */
22 #define FBR2 (0x028) /* DMA Channel 2 Frame Branch Register */
23 #define FBR3 (0x02C) /* DMA Channel 2 Frame Branch Register */
24 #define FBR4 (0x030) /* DMA Channel 2 Frame Branch Register */
25 #define FBR5 (0x110) /* DMA Channel 2 Frame Branch Register */
26 #define FBR6 (0x114) /* DMA Channel 2 Frame Branch Register */
49 #define FDADR0 (0x200) /* DMA Channel 0 Frame Descriptor Address Register */
50 #define FDADR1 (0x210) /* DMA Channel 1 Frame Descriptor Address Register */
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/linux-6.12.1/arch/mips/include/asm/mach-bcm63xx/
Dbcm63xx_dev_enet.h1 /* SPDX-License-Identifier: GPL-2.0 */
44 /* DMA channel enable mask */
47 /* DMA channel interrupt mask */
50 /* DMA engine has internal SRAM */
53 /* DMA channel register width */
56 /* DMA descriptor shift */
59 /* dma channel ids */
89 /* DMA channel enable mask */
92 /* DMA channel interrupt mask */
95 /* DMA channel register width */
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/linux-6.12.1/Documentation/devicetree/bindings/dma/
Dqcom,gpi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/qcom,gpi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies Inc GPI DMA controller
10 - Vinod Koul <vkoul@kernel.org>
13 QCOM GPI DMA controller provides DMA capabilities for
17 - $ref: dma-controller.yaml#
22 - enum:
23 - qcom,sdm845-gpi-dma
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Dbrcm,bcm2835-dma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/brcm,bcm2835-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: BCM2835 DMA controller
10 - Nicolas Saenz Julienne <nsaenz@kernel.org>
13 The BCM2835 DMA controller has 16 channels in total. Only the lower
19 - $ref: dma-controller.yaml#
23 const: brcm,bcm2835-dma
30 Should contain the DMA interrupts associated to the DMA channels in
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Dnvidia,tegra186-gpc-dma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/nvidia,tegra186-gpc-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra GPC DMA Controller
10 The Tegra General Purpose Central (GPC) DMA controller is used for faster
15 - Jon Hunter <jonathanh@nvidia.com>
16 - Rajesh Gumasta <rgumasta@nvidia.com>
19 - $ref: dma-controller.yaml#
24 - const: nvidia,tegra186-gpcdma
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Dintel,ldma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/intel,ldma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Lightning Mountain centralized DMA controllers.
10 - chuanhua.lei@intel.com
11 - mallikarjunax.reddy@intel.com
14 - $ref: dma-controller.yaml#
19 - intel,lgm-cdma
20 - intel,lgm-dma2tx
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/linux-6.12.1/Documentation/driver-api/rapidio/
Dtsi721.rst2 RapidIO subsystem mport driver for IDT Tsi721 PCI Express-to-SRIO bridge.
10 doorbells, inbound maintenance port-writes and RapidIO messaging.
12 To generate SRIO maintenance transactions this driver uses one of Tsi721 DMA
23 - 'dbg_level'
24 - This parameter allows to control amount of debug information
28 For mask definitions see 'drivers/rapidio/devices/tsi721.h'
32 - 'dma_desc_per_channel'
33 - This parameter defines number of hardware buffer
34 descriptors allocated for each registered Tsi721 DMA channel.
37 - 'dma_txqueue_sz'
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/linux-6.12.1/Documentation/arch/arm/stm32/
Dstm32-dma-mdma-chaining.rst1 .. SPDX-License-Identifier: GPL-2.0
4 STM32 DMA-MDMA chaining
9 ------------
11 This document describes the STM32 DMA-MDMA chaining feature. But before going
15 direct memory access controllers (DMA).
17 STM32MP1 SoCs embed both STM32 DMA and STM32 MDMA controllers. STM32 DMA
18 request routing capabilities are enhanced by a DMA request multiplexer
23 STM32 DMAMUX routes any DMA request from a given peripheral to any STM32 DMA
24 controller (STM32MP1 counts two STM32 DMA controllers) channels.
26 **STM32 DMA**
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/linux-6.12.1/arch/mips/include/asm/
Ddma.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
5 * High DMA channel support & info by Hannu Savolainen
9 * and can only be used for expansion cards. Onboard DMA controllers, such
30 * NOTES about DMA transfers:
32 * controller 1: channels 0-3, byte operations, ports 00-1F
33 * controller 2: channels 4-7, word operations, ports C0-DF
35 * - ALL registers are 8 bits only, regardless of transfer size
36 * - channel 4 is not used - cascades 1 into 2.
37 * - channels 0-3 are byte - addresses/counts are for physical bytes
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/linux-6.12.1/arch/x86/include/asm/
Ddma.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
5 * High DMA channel support & info by Hannu Savolainen
24 * NOTES about DMA transfers:
26 * controller 1: channels 0-3, byte operations, ports 00-1F
27 * controller 2: channels 4-7, word operations, ports C0-DF
29 * - ALL registers are 8 bits only, regardless of transfer size
30 * - channel 4 is not used - cascades 1 into 2.
31 * - channels 0-3 are byte - addresses/counts are for physical bytes
32 * - channels 5-7 are word - addresses/counts are for physical words
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/linux-6.12.1/drivers/dma/
Ddmaengine.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
7 * This code implements the DMA subsystem. It provides a HW-neutral interface
9 * if present, and allows different HW DMA drivers to register as providing
21 * A subsystem can get access to a channel by calling dmaengine_get() followed
22 * by dma_find_channel(), or if it has need for an exclusive channel it can call
23 * dma_request_channel(). Once a channel is allocated a reference is taken
29 * See Documentation/driver-api/dmaengine for more details
35 #include <linux/dma-mapping.h>
63 /* --- debugfs implementation --- */
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Dat_xdmac.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for the Atmel Extensible DMA Controller (aka XDMAC on AT91 systems)
11 #include <dt-bindings/dma/at91.h>
54 #define AT_XDMAC_GIM 0x14 /* Global Interrupt Mask Register */
56 #define AT_XDMAC_GE 0x1C /* Global Channel Enable Register */
57 #define AT_XDMAC_GD 0x20 /* Global Channel Disable Register */
58 #define AT_XDMAC_GS 0x24 /* Global Channel Status Register */
61 /* Channel relative registers offsets */
62 #define AT_XDMAC_CIE 0x00 /* Channel Interrupt Enable Register */
70 #define AT_XDMAC_CID 0x04 /* Channel Interrupt Disable Register */
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/linux-6.12.1/sound/soc/fsl/
Dfsl_asrc_dma.c1 // SPDX-License-Identifier: GPL-2.0
3 // Freescale ASRC ALSA SoC Platform (DMA) driver
9 #include <linux/dma-mapping.h>
11 #include <linux/dma/imx-dma.h>
37 chan->private = param; in filter()
45 struct snd_pcm_runtime *runtime = substream->runtime; in fsl_asrc_dma_complete()
46 struct fsl_asrc_pair *pair = runtime->private_data; in fsl_asrc_dma_complete()
48 pair->pos += snd_pcm_lib_period_bytes(substream); in fsl_asrc_dma_complete()
49 if (pair->pos >= snd_pcm_lib_buffer_bytes(substream)) in fsl_asrc_dma_complete()
50 pair->pos = 0; in fsl_asrc_dma_complete()
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/linux-6.12.1/arch/alpha/include/asm/
Ddma.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * include/asm-alpha/dma.h
5 * This is essentially the same as the i386 DMA stuff, as the AlphaPCs
6 * use ISA-compatible dma. The only extension is support for high-page
7 * registers that allow to set the top 8 bits of a 32-bit DMA address.
8 * This register should be written last when setting up a DMA address
9 * as this will also enable DMA across 64 KB boundaries.
12 /* $Id: dma.h,v 1.7 1992/12/14 00:29:34 root Exp root $
13 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
15 * High DMA channel support & info by Hannu Savolainen
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/linux-6.12.1/sound/core/
Dpcm_dmaengine.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Author: Lars-Peter Clausen <lars@metafoo.de>
7 * imx-pcm-dma-mx2.c, Copyright 2009 Sascha Hauer <s.hauer@pengutronix.de>
8 * mxs-pcm.c, Copyright (C) 2011 Freescale Semiconductor, Inc.
9 * ep93xx-pcm.c, Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
32 return substream->runtime->private_data; in substream_to_prtd()
39 return prtd->dma_chan; in snd_dmaengine_pcm_get_chan()
44 * snd_hwparams_to_dma_slave_config - Convert hw_params to dma_slave_config
47 * @slave_config: DMA slave config
63 return -EINVAL; in snd_hwparams_to_dma_slave_config()
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/linux-6.12.1/arch/powerpc/include/asm/
Ddma.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 * Defines for using and allocating dma channels.
9 * High DMA channel support & info by Hannu Savolainen
19 * basically just enough here to get kernel/dma.c to compile.
29 /* The maximum address that we can perform a DMA transfer to on this platform */
42 * NOTES about DMA transfers:
44 * controller 1: channels 0-3, byte operations, ports 00-1F
45 * controller 2: channels 4-7, word operations, ports C0-DF
47 * - ALL registers are 8 bits only, regardless of transfer size
48 * - channel 4 is not used - cascades 1 into 2.
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/linux-6.12.1/drivers/usb/musb/
Dux500_dma.c1 // SPDX-License-Identifier: GPL-2.0+
5 * U8500 DMA support code
8 * Copyright (C) 2011 ST-Ericsson SA
18 #include <linux/dma-mapping.h>
22 #include <linux/platform_data/usb-musb-ux500.h>
31 struct dma_channel channel; member
50 /* Work function invoked from DMA callback to handle rx transfers. */
53 struct dma_channel *channel = private_data; in ux500_dma_callback() local
54 struct ux500_dma_channel *ux500_channel = channel->private_data; in ux500_dma_callback()
55 struct musb_hw_ep *hw_ep = ux500_channel->hw_ep; in ux500_dma_callback()
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/linux-6.12.1/arch/powerpc/boot/dts/fsl/
Dmpc8641si-post.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A.
9 #address-cells = <2>;
10 #size-cells = <1>;
11 compatible = "fsl,mpc8641-localbus", "simple-bus";
16 #address-cells = <1>;
17 #size-cells = <1>;
19 compatible = "fsl,mpc8641-soc", "simple-bus";
20 bus-frequency = <0>;
22 mcm-law@0 {
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/linux-6.12.1/arch/powerpc/boot/dts/
Dmpc8349emitxgp.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MPC8349E-mITX-GP Device Tree Source
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
24 #address-cells = <1>;
25 #size-cells = <0>;
30 d-cache-line-size = <32>;
31 i-cache-line-size = <32>;
32 d-cache-size = <32768>;
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/linux-6.12.1/drivers/net/ethernet/sfc/
Dnic.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2006-2013 Solarflare Communications Inc.
34 buffer->addr = dma_alloc_coherent(&efx->pci_dev->dev, len, in efx_nic_alloc_buffer()
35 &buffer->dma_addr, gfp_flags); in efx_nic_alloc_buffer()
36 if (!buffer->addr) in efx_nic_alloc_buffer()
37 return -ENOMEM; in efx_nic_alloc_buffer()
38 buffer->len = len; in efx_nic_alloc_buffer()
44 if (buffer->addr) { in efx_nic_free_buffer()
45 dma_free_coherent(&efx->pci_dev->dev, buffer->len, in efx_nic_free_buffer()
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/linux-6.12.1/drivers/spi/
Dspi-dw-dma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Special handling for DW DMA core
9 #include <linux/dma-mapping.h>
15 #include <linux/platform_data/dma-dw.h>
19 #include "spi-dw.h"
30 if (s->dma_dev != chan->device->dev) in dw_spi_dma_chan_filter()
33 chan->private = s; in dw_spi_dma_chan_filter()
43 def_burst = dws->fifo_len / 2; in dw_spi_dma_maxburst_init()
45 ret = dma_get_slave_caps(dws->rxchan, &caps); in dw_spi_dma_maxburst_init()
51 dws->rxburst = min(max_burst, def_burst); in dw_spi_dma_maxburst_init()
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/linux-6.12.1/drivers/dma/dw/
Dcore.c1 // SPDX-License-Identifier: GPL-2.0
3 * Core driver for the Synopsys DesignWare DMA Controller
5 * Copyright (C) 2007-2008 Atmel Corporation
6 * Copyright (C) 2010-2011 ST Microelectronics
13 #include <linux/dma-mapping.h>
29 * This supports the Synopsys "DesignWare AHB Central DMA Controller",
35 /* The set of bus widths supported by the DMA controller */
42 /*----------------------------------------------------------------------*/
46 return &chan->dev->device; in chan2dev()
51 return to_dw_desc(dwc->active_list.next); in dwc_first_active()
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