Lines Matching +full:dma +full:- +full:channel +full:- +full:mask
1 // SPDX-License-Identifier: GPL-2.0
3 * Core driver for the Synopsys DesignWare DMA Controller
5 * Copyright (C) 2007-2008 Atmel Corporation
6 * Copyright (C) 2010-2011 ST Microelectronics
13 #include <linux/dma-mapping.h>
29 * This supports the Synopsys "DesignWare AHB Central DMA Controller",
35 /* The set of bus widths supported by the DMA controller */
42 /*----------------------------------------------------------------------*/
46 return &chan->dev->device; in chan2dev()
51 return to_dw_desc(dwc->active_list.next); in dwc_first_active()
57 struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan); in dwc_tx_submit()
61 spin_lock_irqsave(&dwc->lock, flags); in dwc_tx_submit()
67 * for DMA. But this is hard to do in a race-free manner. in dwc_tx_submit()
70 list_add_tail(&desc->desc_node, &dwc->queue); in dwc_tx_submit()
71 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_tx_submit()
72 dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", in dwc_tx_submit()
73 __func__, desc->txd.cookie); in dwc_tx_submit()
80 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in dwc_desc_get()
84 desc = dma_pool_zalloc(dw->desc_pool, GFP_ATOMIC, &phys); in dwc_desc_get()
88 dwc->descs_allocated++; in dwc_desc_get()
89 INIT_LIST_HEAD(&desc->tx_list); in dwc_desc_get()
90 dma_async_tx_descriptor_init(&desc->txd, &dwc->chan); in dwc_desc_get()
91 desc->txd.tx_submit = dwc_tx_submit; in dwc_desc_get()
92 desc->txd.flags = DMA_CTRL_ACK; in dwc_desc_get()
93 desc->txd.phys = phys; in dwc_desc_get()
99 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in dwc_desc_put()
105 list_for_each_entry_safe(child, _next, &desc->tx_list, desc_node) { in dwc_desc_put()
106 list_del(&child->desc_node); in dwc_desc_put()
107 dma_pool_free(dw->desc_pool, child, child->txd.phys); in dwc_desc_put()
108 dwc->descs_allocated--; in dwc_desc_put()
111 dma_pool_free(dw->desc_pool, desc, desc->txd.phys); in dwc_desc_put()
112 dwc->descs_allocated--; in dwc_desc_put()
117 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in dwc_initialize()
119 dw->initialize_chan(dwc); in dwc_initialize()
122 channel_set_bit(dw, MASK.XFER, dwc->mask); in dwc_initialize()
123 channel_set_bit(dw, MASK.ERROR, dwc->mask); in dwc_initialize()
126 /*----------------------------------------------------------------------*/
130 dev_err(chan2dev(&dwc->chan), in dwc_dump_chan_regs()
141 channel_clear_bit(dw, CH_EN, dwc->mask); in dwc_chan_disable()
142 while (dma_readl(dw, CH_EN) & dwc->mask) in dwc_chan_disable()
146 /*----------------------------------------------------------------------*/
152 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in dwc_do_single_block()
165 channel_set_bit(dw, CH_EN, dwc->mask); in dwc_do_single_block()
168 dwc->tx_node_active = dwc->tx_node_active->next; in dwc_do_single_block()
171 /* Called with dwc->lock held and bh disabled */
174 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in dwc_dostart()
175 u8 lms = DWC_LLP_LMS(dwc->dws.m_master); in dwc_dostart()
178 /* ASSERT: channel is idle */ in dwc_dostart()
179 if (dma_readl(dw, CH_EN) & dwc->mask) { in dwc_dostart()
180 dev_err(chan2dev(&dwc->chan), in dwc_dostart()
181 "%s: BUG: Attempted to start non-idle channel\n", in dwc_dostart()
189 if (dwc->nollp) { in dwc_dostart()
191 &dwc->flags); in dwc_dostart()
193 dev_err(chan2dev(&dwc->chan), in dwc_dostart()
200 first->residue = first->total_len; in dwc_dostart()
201 dwc->tx_node_active = &first->tx_list; in dwc_dostart()
211 channel_writel(dwc, LLP, first->txd.phys | lms); in dwc_dostart()
214 channel_set_bit(dw, CH_EN, dwc->mask); in dwc_dostart()
221 if (list_empty(&dwc->queue)) in dwc_dostart_first_queued()
224 list_move(dwc->queue.next, &dwc->active_list); in dwc_dostart_first_queued()
226 dev_vdbg(chan2dev(&dwc->chan), "%s: started %u\n", __func__, desc->txd.cookie); in dwc_dostart_first_queued()
230 /*----------------------------------------------------------------------*/
236 struct dma_async_tx_descriptor *txd = &desc->txd; in dwc_descriptor_complete()
241 dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie); in dwc_descriptor_complete()
243 spin_lock_irqsave(&dwc->lock, flags); in dwc_descriptor_complete()
251 list_for_each_entry(child, &desc->tx_list, desc_node) in dwc_descriptor_complete()
252 async_tx_ack(&child->txd); in dwc_descriptor_complete()
253 async_tx_ack(&desc->txd); in dwc_descriptor_complete()
255 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_descriptor_complete()
266 spin_lock_irqsave(&dwc->lock, flags); in dwc_complete_all()
267 if (dma_readl(dw, CH_EN) & dwc->mask) { in dwc_complete_all()
268 dev_err(chan2dev(&dwc->chan), in dwc_complete_all()
269 "BUG: XFER bit set, but channel not idle!\n"); in dwc_complete_all()
271 /* Try to continue after resetting the channel... */ in dwc_complete_all()
279 list_splice_init(&dwc->active_list, &list); in dwc_complete_all()
282 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_complete_all()
291 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in dwc_get_sent()
295 return dw->block2bytes(dwc, ctlhi, ctllo >> 4 & 7); in dwc_get_sent()
306 spin_lock_irqsave(&dwc->lock, flags); in dwc_scan_descriptors()
310 if (status_xfer & dwc->mask) { in dwc_scan_descriptors()
312 dma_writel(dw, CLEAR.XFER, dwc->mask); in dwc_scan_descriptors()
314 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { in dwc_scan_descriptors()
315 struct list_head *head, *active = dwc->tx_node_active; in dwc_scan_descriptors()
323 head = &desc->tx_list; in dwc_scan_descriptors()
326 if (active == head->next) in dwc_scan_descriptors()
327 desc->residue -= desc->len; in dwc_scan_descriptors()
329 desc->residue -= to_dw_desc(active->prev)->len; in dwc_scan_descriptors()
336 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_scan_descriptors()
341 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); in dwc_scan_descriptors()
344 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_scan_descriptors()
350 if (list_empty(&dwc->active_list)) { in dwc_scan_descriptors()
351 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_scan_descriptors()
355 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { in dwc_scan_descriptors()
356 dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__); in dwc_scan_descriptors()
357 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_scan_descriptors()
361 dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp); in dwc_scan_descriptors()
363 list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) { in dwc_scan_descriptors()
365 desc->residue = desc->total_len; in dwc_scan_descriptors()
368 if (desc->txd.phys == DWC_LLP_LOC(llp)) { in dwc_scan_descriptors()
369 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_scan_descriptors()
376 desc->residue -= dwc_get_sent(dwc); in dwc_scan_descriptors()
377 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_scan_descriptors()
381 desc->residue -= desc->len; in dwc_scan_descriptors()
382 list_for_each_entry(child, &desc->tx_list, desc_node) { in dwc_scan_descriptors()
385 desc->residue -= dwc_get_sent(dwc); in dwc_scan_descriptors()
386 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_scan_descriptors()
389 desc->residue -= child->len; in dwc_scan_descriptors()
396 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_scan_descriptors()
398 spin_lock_irqsave(&dwc->lock, flags); in dwc_scan_descriptors()
401 dev_err(chan2dev(&dwc->chan), in dwc_scan_descriptors()
402 "BUG: All descriptors done, but channel not idle!\n"); in dwc_scan_descriptors()
404 /* Try to continue after resetting the channel... */ in dwc_scan_descriptors()
408 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_scan_descriptors()
413 dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n", in dwc_dump_lli()
429 spin_lock_irqsave(&dwc->lock, flags); in dwc_handle_error()
437 list_del_init(&bad_desc->desc_node); in dwc_handle_error()
438 list_move(dwc->queue.next, dwc->active_list.prev); in dwc_handle_error()
441 dma_writel(dw, CLEAR.ERROR, dwc->mask); in dwc_handle_error()
442 if (!list_empty(&dwc->active_list)) in dwc_handle_error()
452 dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n" in dwc_handle_error()
453 " cookie: %d\n", bad_desc->txd.cookie); in dwc_handle_error()
455 list_for_each_entry(child, &bad_desc->tx_list, desc_node) in dwc_handle_error()
458 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_handle_error()
475 dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err); in dw_dma_tasklet()
477 for (i = 0; i < dw->dma.chancnt; i++) { in dw_dma_tasklet()
478 dwc = &dw->chan[i]; in dw_dma_tasklet()
479 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) in dw_dma_tasklet()
480 dev_vdbg(dw->dma.dev, "Cyclic xfer is not implemented\n"); in dw_dma_tasklet()
487 /* Re-enable interrupts */ in dw_dma_tasklet()
488 channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); in dw_dma_tasklet()
489 channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); in dw_dma_tasklet()
498 if (!dw->in_use) in dw_dma_interrupt()
502 dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status); in dw_dma_interrupt()
512 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); in dw_dma_interrupt()
513 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); in dw_dma_interrupt()
514 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); in dw_dma_interrupt()
518 dev_err(dw->dma.dev, in dw_dma_interrupt()
523 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1); in dw_dma_interrupt()
524 channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1); in dw_dma_interrupt()
525 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1); in dw_dma_interrupt()
526 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1); in dw_dma_interrupt()
527 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1); in dw_dma_interrupt()
530 tasklet_schedule(&dw->tasklet); in dw_dma_interrupt()
535 /*----------------------------------------------------------------------*/
542 struct dw_dma *dw = to_dw_dma(chan->device); in dwc_prep_dma_memcpy()
548 u8 m_master = dwc->dws.m_master; in dwc_prep_dma_memcpy()
551 unsigned int data_width = dw->pdata->data_width[m_master]; in dwc_prep_dma_memcpy()
564 dwc->direction = DMA_MEM_TO_MEM; in dwc_prep_dma_memcpy()
568 ctllo = dw->prepare_ctllo(dwc) in dwc_prep_dma_memcpy()
581 ctlhi = dw->bytes2block(dwc, len - offset, src_width, &xfer_count); in dwc_prep_dma_memcpy()
587 desc->len = xfer_count; in dwc_prep_dma_memcpy()
592 lli_write(prev, llp, desc->txd.phys | lms); in dwc_prep_dma_memcpy()
593 list_add_tail(&desc->desc_node, &first->tx_list); in dwc_prep_dma_memcpy()
602 prev->lli.llp = 0; in dwc_prep_dma_memcpy()
604 first->txd.flags = flags; in dwc_prep_dma_memcpy()
605 first->total_len = len; in dwc_prep_dma_memcpy()
607 return &first->txd; in dwc_prep_dma_memcpy()
620 struct dw_dma *dw = to_dw_dma(chan->device); in dwc_prep_slave_sg()
621 struct dma_slave_config *sconfig = &dwc->dma_sconfig; in dwc_prep_slave_sg()
625 u8 lms = DWC_LLP_LMS(dwc->dws.m_master); in dwc_prep_slave_sg()
638 dwc->direction = direction; in dwc_prep_slave_sg()
644 reg_width = __ffs(sconfig->dst_addr_width); in dwc_prep_slave_sg()
645 reg = sconfig->dst_addr; in dwc_prep_slave_sg()
646 ctllo = dw->prepare_ctllo(dwc) in dwc_prep_slave_sg()
651 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) : in dwc_prep_slave_sg()
662 mem_width = __ffs(sconfig->src_addr_width | mem | len); in dwc_prep_slave_sg()
669 ctlhi = dw->bytes2block(dwc, len, mem_width, &dlen); in dwc_prep_slave_sg()
675 desc->len = dlen; in dwc_prep_slave_sg()
680 lli_write(prev, llp, desc->txd.phys | lms); in dwc_prep_slave_sg()
681 list_add_tail(&desc->desc_node, &first->tx_list); in dwc_prep_slave_sg()
686 len -= dlen; in dwc_prep_slave_sg()
694 reg_width = __ffs(sconfig->src_addr_width); in dwc_prep_slave_sg()
695 reg = sconfig->src_addr; in dwc_prep_slave_sg()
696 ctllo = dw->prepare_ctllo(dwc) in dwc_prep_slave_sg()
701 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) : in dwc_prep_slave_sg()
717 ctlhi = dw->bytes2block(dwc, len, reg_width, &dlen); in dwc_prep_slave_sg()
722 mem_width = __ffs(sconfig->dst_addr_width | mem); in dwc_prep_slave_sg()
724 desc->len = dlen; in dwc_prep_slave_sg()
729 lli_write(prev, llp, desc->txd.phys | lms); in dwc_prep_slave_sg()
730 list_add_tail(&desc->desc_node, &first->tx_list); in dwc_prep_slave_sg()
735 len -= dlen; in dwc_prep_slave_sg()
750 prev->lli.llp = 0; in dwc_prep_slave_sg()
752 first->total_len = total_len; in dwc_prep_slave_sg()
754 return &first->txd; in dwc_prep_slave_sg()
768 if (dws->dma_dev != chan->device->dev) in dw_dma_filter()
771 /* permit channels in accordance with the channels mask */ in dw_dma_filter()
772 if (dws->channels && !(dws->channels & dwc->mask)) in dw_dma_filter()
776 memcpy(&dwc->dws, dws, sizeof(struct dw_dma_slave)); in dw_dma_filter()
786 dwc->dma_sconfig.src_maxburst = in dwc_verify_maxburst()
787 clamp(dwc->dma_sconfig.src_maxburst, 1U, dwc->max_burst); in dwc_verify_maxburst()
788 dwc->dma_sconfig.dst_maxburst = in dwc_verify_maxburst()
789 clamp(dwc->dma_sconfig.dst_maxburst, 1U, dwc->max_burst); in dwc_verify_maxburst()
791 dwc->dma_sconfig.src_maxburst = in dwc_verify_maxburst()
792 rounddown_pow_of_two(dwc->dma_sconfig.src_maxburst); in dwc_verify_maxburst()
793 dwc->dma_sconfig.dst_maxburst = in dwc_verify_maxburst()
794 rounddown_pow_of_two(dwc->dma_sconfig.dst_maxburst); in dwc_verify_maxburst()
802 struct dw_dma *dw = to_dw_dma(chan->device); in dwc_verify_p_buswidth()
805 if (dwc->dma_sconfig.direction == DMA_MEM_TO_DEV) in dwc_verify_p_buswidth()
806 reg_width = dwc->dma_sconfig.dst_addr_width; in dwc_verify_p_buswidth()
807 else if (dwc->dma_sconfig.direction == DMA_DEV_TO_MEM) in dwc_verify_p_buswidth()
808 reg_width = dwc->dma_sconfig.src_addr_width; in dwc_verify_p_buswidth()
812 max_width = dw->pdata->data_width[dwc->dws.p_master]; in dwc_verify_p_buswidth()
814 /* Fall-back to 1-byte transfer width if undefined */ in dwc_verify_p_buswidth()
818 return -EINVAL; in dwc_verify_p_buswidth()
823 if (dwc->dma_sconfig.direction == DMA_MEM_TO_DEV) in dwc_verify_p_buswidth()
824 dwc->dma_sconfig.dst_addr_width = reg_width; in dwc_verify_p_buswidth()
826 dwc->dma_sconfig.src_addr_width = reg_width; in dwc_verify_p_buswidth()
834 struct dw_dma *dw = to_dw_dma(chan->device); in dwc_verify_m_buswidth()
837 mem_width = dw->pdata->data_width[dwc->dws.m_master]; in dwc_verify_m_buswidth()
840 * It's possible to have a data portion locked in the DMA FIFO in case in dwc_verify_m_buswidth()
841 * of the channel suspension. Subsequent channel disabling will cause in dwc_verify_m_buswidth()
847 * Note the DMA configs utilized in the calculations below must have in dwc_verify_m_buswidth()
850 if (dwc->dma_sconfig.direction == DMA_MEM_TO_DEV) { in dwc_verify_m_buswidth()
851 reg_width = dwc->dma_sconfig.dst_addr_width; in dwc_verify_m_buswidth()
853 return -EINVAL; in dwc_verify_m_buswidth()
855 dwc->dma_sconfig.src_addr_width = mem_width; in dwc_verify_m_buswidth()
856 } else if (dwc->dma_sconfig.direction == DMA_DEV_TO_MEM) { in dwc_verify_m_buswidth()
857 reg_width = dwc->dma_sconfig.src_addr_width; in dwc_verify_m_buswidth()
858 reg_burst = dwc->dma_sconfig.src_maxburst; in dwc_verify_m_buswidth()
860 dwc->dma_sconfig.dst_addr_width = min(mem_width, reg_width * reg_burst); in dwc_verify_m_buswidth()
871 memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig)); in dwc_config()
890 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in dwc_chan_pause()
893 dw->suspend_chan(dwc, drain); in dwc_chan_pause()
895 while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--) in dwc_chan_pause()
898 set_bit(DW_DMA_IS_PAUSED, &dwc->flags); in dwc_chan_pause()
906 spin_lock_irqsave(&dwc->lock, flags); in dwc_pause()
908 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_pause()
915 struct dw_dma *dw = to_dw_dma(dwc->chan.device); in dwc_chan_resume()
917 dw->resume_chan(dwc, drain); in dwc_chan_resume()
919 clear_bit(DW_DMA_IS_PAUSED, &dwc->flags); in dwc_chan_resume()
927 spin_lock_irqsave(&dwc->lock, flags); in dwc_resume()
929 if (test_bit(DW_DMA_IS_PAUSED, &dwc->flags)) in dwc_resume()
932 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_resume()
940 struct dw_dma *dw = to_dw_dma(chan->device); in dwc_terminate_all()
945 spin_lock_irqsave(&dwc->lock, flags); in dwc_terminate_all()
947 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); in dwc_terminate_all()
956 list_splice_init(&dwc->queue, &list); in dwc_terminate_all()
957 list_splice_init(&dwc->active_list, &list); in dwc_terminate_all()
959 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_terminate_all()
972 list_for_each_entry(desc, &dwc->active_list, desc_node) in dwc_find_desc()
973 if (desc->txd.cookie == c) in dwc_find_desc()
986 spin_lock_irqsave(&dwc->lock, flags); in dwc_get_residue_and_status()
991 residue = desc->residue; in dwc_get_residue_and_status()
992 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue) in dwc_get_residue_and_status()
993 residue -= dwc_get_sent(dwc); in dwc_get_residue_and_status()
994 if (test_bit(DW_DMA_IS_PAUSED, &dwc->flags)) in dwc_get_residue_and_status()
997 residue = desc->total_len; in dwc_get_residue_and_status()
1003 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_get_residue_and_status()
1019 dwc_scan_descriptors(to_dw_dma(chan->device), dwc); in dwc_tx_status()
1034 spin_lock_irqsave(&dwc->lock, flags); in dwc_issue_pending()
1035 if (list_empty(&dwc->active_list)) in dwc_issue_pending()
1037 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_issue_pending()
1040 /*----------------------------------------------------------------------*/
1046 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); in do_dw_dma_off()
1047 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); in do_dw_dma_off()
1048 channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); in do_dw_dma_off()
1049 channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); in do_dw_dma_off()
1050 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); in do_dw_dma_off()
1064 struct dw_dma *dw = to_dw_dma(chan->device); in dwc_alloc_chan_resources()
1068 /* ASSERT: channel is idle */ in dwc_alloc_chan_resources()
1069 if (dma_readl(dw, CH_EN) & dwc->mask) { in dwc_alloc_chan_resources()
1070 dev_dbg(chan2dev(chan), "DMA channel not idle?\n"); in dwc_alloc_chan_resources()
1071 return -EIO; in dwc_alloc_chan_resources()
1078 * need to initialize here, like "scatter-gather" (which in dwc_alloc_chan_resources()
1083 * We need controller-specific data to set up slave transfers. in dwc_alloc_chan_resources()
1085 if (chan->private && !dw_dma_filter(chan, chan->private)) { in dwc_alloc_chan_resources()
1086 dev_warn(chan2dev(chan), "Wrong controller-specific data\n"); in dwc_alloc_chan_resources()
1087 return -EINVAL; in dwc_alloc_chan_resources()
1091 if (!dw->in_use) in dwc_alloc_chan_resources()
1093 dw->in_use |= dwc->mask; in dwc_alloc_chan_resources()
1101 struct dw_dma *dw = to_dw_dma(chan->device); in dwc_free_chan_resources()
1105 dwc->descs_allocated); in dwc_free_chan_resources()
1107 /* ASSERT: channel is idle */ in dwc_free_chan_resources()
1108 BUG_ON(!list_empty(&dwc->active_list)); in dwc_free_chan_resources()
1109 BUG_ON(!list_empty(&dwc->queue)); in dwc_free_chan_resources()
1110 BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask); in dwc_free_chan_resources()
1112 spin_lock_irqsave(&dwc->lock, flags); in dwc_free_chan_resources()
1114 /* Clear custom channel configuration */ in dwc_free_chan_resources()
1115 memset(&dwc->dws, 0, sizeof(struct dw_dma_slave)); in dwc_free_chan_resources()
1118 channel_clear_bit(dw, MASK.XFER, dwc->mask); in dwc_free_chan_resources()
1119 channel_clear_bit(dw, MASK.BLOCK, dwc->mask); in dwc_free_chan_resources()
1120 channel_clear_bit(dw, MASK.ERROR, dwc->mask); in dwc_free_chan_resources()
1122 spin_unlock_irqrestore(&dwc->lock, flags); in dwc_free_chan_resources()
1125 dw->in_use &= ~dwc->mask; in dwc_free_chan_resources()
1126 if (!dw->in_use) in dwc_free_chan_resources()
1136 caps->max_burst = dwc->max_burst; in dwc_caps()
1140 * accelerated multi-block transfers supported, aka LLPs in DW DMAC in dwc_caps()
1143 * single DMA transaction, otherwise it's just one SG entry. in dwc_caps()
1145 if (dwc->nollp) in dwc_caps()
1146 caps->max_sg_burst = 1; in dwc_caps()
1148 caps->max_sg_burst = 0; in dwc_caps()
1153 struct dw_dma *dw = chip->dw; in do_dma_probe()
1160 dw->pdata = devm_kzalloc(chip->dev, sizeof(*dw->pdata), GFP_KERNEL); in do_dma_probe()
1161 if (!dw->pdata) in do_dma_probe()
1162 return -ENOMEM; in do_dma_probe()
1164 dw->regs = chip->regs; in do_dma_probe()
1166 pm_runtime_get_sync(chip->dev); in do_dma_probe()
1168 if (!chip->pdata) { in do_dma_probe()
1170 dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params); in do_dma_probe()
1174 ret = -EINVAL; in do_dma_probe()
1179 pdata = dw->pdata; in do_dma_probe()
1182 pdata->nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 7) + 1; in do_dma_probe()
1183 pdata->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1; in do_dma_probe()
1184 for (i = 0; i < pdata->nr_masters; i++) { in do_dma_probe()
1185 pdata->data_width[i] = in do_dma_probe()
1188 pdata->block_size = dma_readl(dw, MAX_BLK_SIZE); in do_dma_probe()
1191 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING; in do_dma_probe()
1192 pdata->chan_priority = CHAN_PRIORITY_ASCENDING; in do_dma_probe()
1193 } else if (chip->pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) { in do_dma_probe()
1194 ret = -EINVAL; in do_dma_probe()
1197 memcpy(dw->pdata, chip->pdata, sizeof(*dw->pdata)); in do_dma_probe()
1200 pdata = dw->pdata; in do_dma_probe()
1203 dw->chan = devm_kcalloc(chip->dev, pdata->nr_channels, sizeof(*dw->chan), in do_dma_probe()
1205 if (!dw->chan) { in do_dma_probe()
1206 ret = -ENOMEM; in do_dma_probe()
1210 /* Calculate all channel mask before DMA setup */ in do_dma_probe()
1211 dw->all_chan_mask = (1 << pdata->nr_channels) - 1; in do_dma_probe()
1213 /* Force dma off, just in case */ in do_dma_probe()
1214 dw->disable(dw); in do_dma_probe()
1216 /* Device and instance ID for IRQ and DMA pool */ in do_dma_probe()
1217 dw->set_device_name(dw, chip->id); in do_dma_probe()
1220 dw->desc_pool = dmam_pool_create(dw->name, chip->dev, in do_dma_probe()
1222 if (!dw->desc_pool) { in do_dma_probe()
1223 dev_err(chip->dev, "No memory for descriptors dma pool\n"); in do_dma_probe()
1224 ret = -ENOMEM; in do_dma_probe()
1228 tasklet_setup(&dw->tasklet, dw_dma_tasklet); in do_dma_probe()
1230 ret = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED, in do_dma_probe()
1231 dw->name, dw); in do_dma_probe()
1235 INIT_LIST_HEAD(&dw->dma.channels); in do_dma_probe()
1236 for (i = 0; i < pdata->nr_channels; i++) { in do_dma_probe()
1237 struct dw_dma_chan *dwc = &dw->chan[i]; in do_dma_probe()
1239 dwc->chan.device = &dw->dma; in do_dma_probe()
1240 dma_cookie_init(&dwc->chan); in do_dma_probe()
1241 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING) in do_dma_probe()
1242 list_add_tail(&dwc->chan.device_node, in do_dma_probe()
1243 &dw->dma.channels); in do_dma_probe()
1245 list_add(&dwc->chan.device_node, &dw->dma.channels); in do_dma_probe()
1248 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING) in do_dma_probe()
1249 dwc->priority = pdata->nr_channels - i - 1; in do_dma_probe()
1251 dwc->priority = i; in do_dma_probe()
1253 dwc->ch_regs = &__dw_regs(dw)->CHAN[i]; in do_dma_probe()
1254 spin_lock_init(&dwc->lock); in do_dma_probe()
1255 dwc->mask = 1 << i; in do_dma_probe()
1257 INIT_LIST_HEAD(&dwc->active_list); in do_dma_probe()
1258 INIT_LIST_HEAD(&dwc->queue); in do_dma_probe()
1260 channel_clear_bit(dw, CH_EN, dwc->mask); in do_dma_probe()
1262 dwc->direction = DMA_TRANS_NONE; in do_dma_probe()
1266 unsigned int r = DW_DMA_MAX_NR_CHANNELS - i - 1; in do_dma_probe()
1267 void __iomem *addr = &__dw_regs(dw)->DWC_PARAMS[r]; in do_dma_probe()
1270 dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i, in do_dma_probe()
1274 * Decode maximum block size for given channel. The in do_dma_probe()
1278 dwc->block_size = in do_dma_probe()
1279 (4 << ((pdata->block_size >> 4 * i) & 0xf)) - 1; in do_dma_probe()
1282 * According to the DW DMA databook the true scatter- in do_dma_probe()
1283 * gether LLPs aren't available if either multi-block in do_dma_probe()
1285 * LLP register is hard-coded to zeros in do_dma_probe()
1288 dwc->nollp = in do_dma_probe()
1291 dwc->max_burst = in do_dma_probe()
1294 dwc->block_size = pdata->block_size; in do_dma_probe()
1295 dwc->nollp = !pdata->multi_block[i]; in do_dma_probe()
1296 dwc->max_burst = pdata->max_burst[i] ?: DW_DMA_MAX_BURST; in do_dma_probe()
1301 dma_writel(dw, CLEAR.XFER, dw->all_chan_mask); in do_dma_probe()
1302 dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask); in do_dma_probe()
1303 dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask); in do_dma_probe()
1304 dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask); in do_dma_probe()
1305 dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask); in do_dma_probe()
1308 dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); in do_dma_probe()
1309 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask); in do_dma_probe()
1310 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); in do_dma_probe()
1312 dw->dma.dev = chip->dev; in do_dma_probe()
1313 dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources; in do_dma_probe()
1314 dw->dma.device_free_chan_resources = dwc_free_chan_resources; in do_dma_probe()
1316 dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy; in do_dma_probe()
1317 dw->dma.device_prep_slave_sg = dwc_prep_slave_sg; in do_dma_probe()
1319 dw->dma.device_caps = dwc_caps; in do_dma_probe()
1320 dw->dma.device_config = dwc_config; in do_dma_probe()
1321 dw->dma.device_pause = dwc_pause; in do_dma_probe()
1322 dw->dma.device_resume = dwc_resume; in do_dma_probe()
1323 dw->dma.device_terminate_all = dwc_terminate_all; in do_dma_probe()
1325 dw->dma.device_tx_status = dwc_tx_status; in do_dma_probe()
1326 dw->dma.device_issue_pending = dwc_issue_pending; in do_dma_probe()
1328 /* DMA capabilities */ in do_dma_probe()
1329 dw->dma.min_burst = DW_DMA_MIN_BURST; in do_dma_probe()
1330 dw->dma.max_burst = DW_DMA_MAX_BURST; in do_dma_probe()
1331 dw->dma.src_addr_widths = DW_DMA_BUSWIDTHS; in do_dma_probe()
1332 dw->dma.dst_addr_widths = DW_DMA_BUSWIDTHS; in do_dma_probe()
1333 dw->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) | in do_dma_probe()
1335 dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; in do_dma_probe()
1340 * size as the block size found for the very first channel. in do_dma_probe()
1342 dma_set_max_seg_size(dw->dma.dev, dw->chan[0].block_size); in do_dma_probe()
1344 ret = dma_async_device_register(&dw->dma); in do_dma_probe()
1348 dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n", in do_dma_probe()
1349 pdata->nr_channels); in do_dma_probe()
1351 pm_runtime_put_sync_suspend(chip->dev); in do_dma_probe()
1356 free_irq(chip->irq, dw); in do_dma_probe()
1358 pm_runtime_put_sync_suspend(chip->dev); in do_dma_probe()
1364 struct dw_dma *dw = chip->dw; in do_dma_remove()
1367 pm_runtime_get_sync(chip->dev); in do_dma_remove()
1370 dma_async_device_unregister(&dw->dma); in do_dma_remove()
1372 free_irq(chip->irq, dw); in do_dma_remove()
1373 tasklet_kill(&dw->tasklet); in do_dma_remove()
1375 list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels, in do_dma_remove()
1377 list_del(&dwc->chan.device_node); in do_dma_remove()
1378 channel_clear_bit(dw, CH_EN, dwc->mask); in do_dma_remove()
1381 pm_runtime_put_sync_suspend(chip->dev); in do_dma_remove()
1387 struct dw_dma *dw = chip->dw; in do_dw_dma_disable()
1389 dw->disable(dw); in do_dw_dma_disable()
1396 struct dw_dma *dw = chip->dw; in do_dw_dma_enable()
1398 dw->enable(dw); in do_dw_dma_enable()
1404 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver");