video/fbdev/pxa3xx-regs.h

1 /* SPDX-License-Identifier: GPL-2.0 */
20 #define FBR0		(0x020)	/* DMA Channel 0 Frame Branch Register */
21 #define FBR1		(0x024)	/* DMA Channel 1 Frame Branch Register */
22 #define FBR2		(0x028) /* DMA Channel 2 Frame Branch Register */
23 #define FBR3		(0x02C) /* DMA Channel 2 Frame Branch Register */
24 #define FBR4		(0x030) /* DMA Channel 2 Frame Branch Register */
25 #define FBR5		(0x110) /* DMA Channel 2 Frame Branch Register */
26 #define FBR6		(0x114) /* DMA Channel 2 Frame Branch Register */
49 #define FDADR0		(0x200)	/* DMA Channel 0 Frame Descriptor Address Register */
50 #define FDADR1		(0x210)	/* DMA Channel 1 Frame Descriptor Address Register */
51 #define FDADR2		(0x220)	/* DMA Channel 2 Frame Descriptor Address Register */
52 #define FDADR3		(0x230)	/* DMA Channel 3 Frame Descriptor Address Register */
53 #define FDADR4		(0x240)	/* DMA Channel 4 Frame Descriptor Address Register */
54 #define FDADR5		(0x250)	/* DMA Channel 5 Frame Descriptor Address Register */
55 #define FDADR6		(0x260) /* DMA Channel 6 Frame Descriptor Address Register */
65 #define LCCR0_LDM	(1 << 3)	/* LCD Disable Done Mask */
66 #define LCCR0_SFM	(1 << 4)	/* Start of frame mask */
67 #define LCCR0_IUM	(1 << 5)	/* Input FIFO underrun mask */
68 #define LCCR0_EFM	(1 << 6)	/* End of Frame mask */
73 #define LCCR0_4PixMono	(LCCR0_DPD*0)	/*  4-Pixel/clock Monochrome display */
74 #define LCCR0_8PixMono	(LCCR0_DPD*1)	/*  8-Pixel/clock Monochrome display */
76 #define LCCR0_QDM	(1 << 11)	/* LCD Quick Disable mask */
77 #define LCCR0_PDD	(0xff << 12)	/* Palette DMA request delay */
79 #define LCCR0_BM	(1 << 20)	/* Branch mask */
80 #define LCCR0_OUM	(1 << 21)	/* Output FIFO underrun mask */
82 #define LCCR0_RDSTM	(1 << 23)	/* Read status interrupt mask */
83 #define LCCR0_CMDIM	(1 << 24)	/* Command interrupt mask */
90 #define LCCR1_PPL	Fld (10, 0)	/* Pixels Per Line - 1 */
91 #define LCCR1_DisWdth(Pixel)	(((Pixel) - 1) << FShft (LCCR1_PPL))
94 #define LCCR1_HorSnchWdth(Tpix)	(((Tpix) - 1) << FShft (LCCR1_HSW))
96 #define LCCR1_ELW	Fld (8, 16)	/* End-of-Line pixel clock Wait - 1 */
97 #define LCCR1_EndLnDel(Tpix)	(((Tpix) - 1) << FShft (LCCR1_ELW))
99 #define LCCR1_BLW	Fld (8, 24)	/* Beginning-of-Line pixel clock */
100 #define LCCR1_BegLnDel(Tpix)	(((Tpix) - 1) << FShft (LCCR1_BLW))
102 #define LCCR2_LPP	Fld (10, 0)	/* Line Per Panel - 1 */
103 #define LCCR2_DisHght(Line)	(((Line) - 1) << FShft (LCCR2_LPP))
105 #define LCCR2_VSW	Fld (6, 10)	/* Vertical Synchronization pulse - 1 */
106 #define LCCR2_VrtSnchWdth(Tln)	(((Tln) - 1) << FShft (LCCR2_VSW))
108 #define LCCR2_EFW	Fld (8, 16)	/* End-of-Frame line clock Wait */
111 #define LCCR2_BFW	Fld (8, 24)	/* Beginning-of-Frame line clock */
119 #define LCCR3_PixRsEdg	(LCCR3_PCP*0)	/*  Pixel clock Rising-Edge */
120 #define LCCR3_PixFlEdg	(LCCR3_PCP*1)	/*  Pixel clock Falling-Edge */
139 #define LCCR5_IUM(x)	(1 << ((x) + 23)) /* input underrun mask */
140 #define LCCR5_BSM(x)	(1 << ((x) + 15)) /* branch mask */
141 #define LCCR5_EOFM(x)	(1 << ((x) + 7))  /* end of frame mask */
142 #define LCCR5_SOFM(x)	(1 << ((x) + 0))  /* start of frame mask */
161 #define LCSR1_SOF(x)	(1 << ((x) - 1))  /* Start of Frame Status */
163 #define LDCMD_PAL	(1 << 26)	/* instructs DMA to load palette buffer */
166 #define OVLxC1_PPL(x)	((((x) - 1) & 0x3ff) << 0)	/* Pixels Per Line */
167 #define OVLxC1_LPO(x)	((((x) - 1) & 0x3ff) << 10)	/* Number of Lines */