include/asm/dma.h

1 /* SPDX-License-Identifier: GPL-2.0 */
3  * linux/include/asm/dma.h: Defines for using and allocating dma channels.
5  * High DMA channel support & info by Hannu Savolainen
9  * and can only be used for expansion cards. Onboard DMA controllers, such
30  * NOTES about DMA transfers:
32  *  controller 1: channels 0-3, byte operations, ports 00-1F
33  *  controller 2: channels 4-7, word operations, ports C0-DF
35  *  - ALL registers are 8 bits only, regardless of transfer size
36  *  - channel 4 is not used - cascades 1 into 2.
37  *  - channels 0-3 are byte - addresses/counts are for physical bytes
38  *  - channels 5-7 are word - addresses/counts are for physical words
39  *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
40  *  - transfer count loaded to registers is 1 less than actual count
41  *  - controller 2 offsets are all even (2x offsets for controller 1)
42  *  - page registers for 5-7 don't use data bit 0, represent 128K pages
43  *  - page registers for 0-3 use bit 0, represent 64K pages
45  * DMA transfers are limited to the lower 16MB of _physical_ memory.
49  *  Address mapping for channels 0-3:
56  * |	Page	| Addr MSB | Addr LSB |	  (DMA registers)
58  *  Address mapping for channels 5-7:
65  * |	  Page	    |  Addr MSB	  |  Addr LSB  |   (DMA registers)
67  * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
68  * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
69  * the hardware level, so odd-byte transfers aren't possible).
72  * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
73  * and up to 128K bytes may be transferred on channels 5-7 in one operation.
82  * The maximum address in KSEG0 that we can perform a DMA transfer to on this
83  * platform.  This describes only the PC style part of the DMA logic like on
84  * Deskstations or Acer PICA but not the much more versatile DMA logic used
88 /* don't care; ISA bus master won't work, ISA slave DMA supports 32bit addr */
96 #define MAX_DMA32_PFN		(1UL << (32 - PAGE_SHIFT))
99 /* 8237 DMA controllers */
100 #define IO_DMA1_BASE	0x00	/* 8 bit slave DMA, channels 0..3 */
101 #define IO_DMA2_BASE	0xC0	/* 16 bit master DMA, ch 4(=slave input)..7 */
103 /* DMA controller registers */
107 #define DMA1_MASK_REG		0x0A	/* single-channel mask (w) */
109 #define DMA1_CLEAR_FF_REG	0x0C	/* clear pointer flip-flop (w) */
112 #define DMA1_CLR_MASK_REG	0x0E	/* Clear Mask */
113 #define DMA1_MASK_ALL_REG	0x0F	/* all-channels mask (w) */
118 #define DMA2_MASK_REG		0xD4	/* single-channel mask (w) */
120 #define DMA2_CLEAR_FF_REG	0xD8	/* clear pointer flip-flop (w) */
123 #define DMA2_CLR_MASK_REG	0xDC	/* Clear Mask */
124 #define DMA2_MASK_ALL_REG	0xDE	/* all-channels mask (w) */
126 #define DMA_ADDR_0		0x00	/* DMA address registers */
135 #define DMA_CNT_0		0x01	/* DMA count registers */
144 #define DMA_PAGE_0		0x87	/* DMA page registers */
154 #define DMA_MODE_CASCADE 0xC0	/* pass thru DREQ->HRQ, DACK<-HLDA only */
172 /* enable/disable a specific DMA channel */
189 /* Clear the 'DMA Pointer Flip Flop'.
192  * After that, keep track of it. :-)
193  * --- In order to do that, the DMA routines below should ---
194  * --- only be used while holding the DMA lock ! ---
204 /* set mode (above) for a specific DMA channel */
215  * the lower 16 bits of the DMA current address register, but a 64k boundary
246 /* Set transfer address & page bits for specific DMA channel.
247  * Assumes dma flipflop is clear.
263  * a specific DMA channel.
267  * Assumes dma flip-flop is clear.
268  * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
272 	count--;  in set_dma_count()
283 /* Get DMA residue count. After a DMA transfer, this
284  * should return zero. Reading this while a DMA transfer is
286  * If called before the channel has been used, it may return 1.
289  * Assumes DMA flip-flop is clear.
296 	/* using short to get 16-bit wrap around */  in get_dma_residue()
306 /* These are in kernel/dma.c: */
307 extern int request_dma(unsigned int dmanr, const char * device_id);	/* reserve a DMA channel */