include/asm/dma.h

1 /* SPDX-License-Identifier: GPL-2.0 */
3  * linux/include/asm/dma.h: Defines for using and allocating dma channels.
5  * High DMA channel support & info by Hannu Savolainen
24  * NOTES about DMA transfers:
26  *  controller 1: channels 0-3, byte operations, ports 00-1F
27  *  controller 2: channels 4-7, word operations, ports C0-DF
29  *  - ALL registers are 8 bits only, regardless of transfer size
30  *  - channel 4 is not used - cascades 1 into 2.
31  *  - channels 0-3 are byte - addresses/counts are for physical bytes
32  *  - channels 5-7 are word - addresses/counts are for physical words
33  *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
34  *  - transfer count loaded to registers is 1 less than actual count
35  *  - controller 2 offsets are all even (2x offsets for controller 1)
36  *  - page registers for 5-7 don't use data bit 0, represent 128K pages
37  *  - page registers for 0-3 use bit 0, represent 64K pages
39  * DMA transfers are limited to the lower 16MB of _physical_ memory.
43  *  Address mapping for channels 0-3:
50  * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
52  *  Address mapping for channels 5-7:
59  * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
61  * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
62  * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
63  * the hardware level, so odd-byte transfers aren't possible).
66  * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
67  * and up to 128K bytes may be transferred on channels 5-7 in one operation.
73 /* 16MB ISA DMA zone */
77 #define MAX_DMA32_PFN (1UL << (32 - PAGE_SHIFT))
80 /* The maximum address that we can perform a DMA transfer to on this platform */
83 /* Compat define for old dma zone */
87 /* 8237 DMA controllers */
88 #define IO_DMA1_BASE	0x00	/* 8 bit slave DMA, channels 0..3 */
89 #define IO_DMA2_BASE	0xC0	/* 16 bit master DMA, ch 4(=slave input)..7 */
91 /* DMA controller registers */
95 #define DMA1_MASK_REG		0x0A	/* single-channel mask (w) */
97 #define DMA1_CLEAR_FF_REG	0x0C	/* clear pointer flip-flop (w) */
100 #define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
101 #define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */
106 #define DMA2_MASK_REG		0xD4	/* single-channel mask (w) */
108 #define DMA2_CLEAR_FF_REG	0xD8	/* clear pointer flip-flop (w) */
111 #define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
112 #define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */
114 #define DMA_ADDR_0		0x00    /* DMA address registers */
123 #define DMA_CNT_0		0x01    /* DMA count registers */
132 #define DMA_PAGE_0		0x87    /* DMA page registers */
144 /* pass thru DREQ->HRQ, DACK<-HLDA only */
166 /* enable/disable a specific DMA channel */
183 /* Clear the 'DMA Pointer Flip Flop'.
186  * After that, keep track of it. :-)
187  * --- In order to do that, the DMA routines below should ---
188  * --- only be used while holding the DMA lock ! ---
198 /* set mode (above) for a specific DMA channel */
209  * the lower 16 bits of the DMA current address register, but a 64k boundary
240 /* Set transfer address & page bits for specific DMA channel.
241  * Assumes dma flipflop is clear.
257  * a specific DMA channel.
261  * Assumes dma flip-flop is clear.
262  * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
266 	count--;  in set_dma_count()
280 /* Get DMA residue count. After a DMA transfer, this
281  * should return zero. Reading this while a DMA transfer is
283  * If called before the channel has been used, it may return 1.
286  * Assumes DMA flip-flop is clear.
291 	/* using short to get 16-bit wrap around */  in get_dma_residue()
304 /* These are in kernel/dma.c because x86 uses CONFIG_GENERIC_ISA_DMA */