include/asm/dma.h

1 /* SPDX-License-Identifier: GPL-2.0 */
7  * Defines for using and allocating dma channels.
9  * High DMA channel support & info by Hannu Savolainen
19  * basically just enough here to get kernel/dma.c to compile.
29 /* The maximum address that we can perform a DMA transfer to on this platform */
42  * NOTES about DMA transfers:
44  *  controller 1: channels 0-3, byte operations, ports 00-1F
45  *  controller 2: channels 4-7, word operations, ports C0-DF
47  *  - ALL registers are 8 bits only, regardless of transfer size
48  *  - channel 4 is not used - cascades 1 into 2.
49  *  - channels 0-3 are byte - addresses/counts are for physical bytes
50  *  - channels 5-7 are word - addresses/counts are for physical words
51  *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
52  *  - transfer count loaded to registers is 1 less than actual count
53  *  - controller 2 offsets are all even (2x offsets for controller 1)
54  *  - page registers for 5-7 don't use data bit 0, represent 128K pages
55  *  - page registers for 0-3 use bit 0, represent 64K pages
61  *  Address mapping for channels 0-3:
68  * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
70  *  Address mapping for channels 5-7:
77  * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
79  * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
80  * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
81  * the hardware level, so odd-byte transfers aren't possible).
84  * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
85  * and up to 128K bytes may be transferred on channels 5-7 in one operation.
89 /* 8237 DMA controllers */
90 #define IO_DMA1_BASE	0x00	/* 8 bit slave DMA, channels 0..3 */
91 #define IO_DMA2_BASE	0xC0	/* 16 bit master DMA, ch 4(=slave input)..7 */
93 /* DMA controller registers */
97 #define DMA1_MASK_REG		0x0A	/* single-channel mask (w) */
99 #define DMA1_CLEAR_FF_REG	0x0C	/* clear pointer flip-flop (w) */
102 #define DMA1_CLR_MASK_REG	0x0E	/* Clear Mask */
103 #define DMA1_MASK_ALL_REG	0x0F	/* all-channels mask (w) */
108 #define DMA2_MASK_REG		0xD4	/* single-channel mask (w) */
110 #define DMA2_CLEAR_FF_REG	0xD8	/* clear pointer flip-flop (w) */
113 #define DMA2_CLR_MASK_REG	0xDC	/* Clear Mask */
114 #define DMA2_MASK_ALL_REG	0xDE	/* all-channels mask (w) */
116 #define DMA_ADDR_0		0x00	/* DMA address registers */
125 #define DMA_CNT_0		0x01	/* DMA count registers */
134 #define DMA_LO_PAGE_0		0x87	/* DMA page registers */
142 #define DMA_HI_PAGE_0		0x487	/* DMA page registers */
154     /* in arch/powerpc/kernel/setup_32.c -- Cort */
162 #define DMA_MODE_CASCADE	0xC0	/* pass thru DREQ->HRQ, DACK<-HLDA only */
180 /* enable/disable a specific DMA channel */
205 /* Clear the 'DMA Pointer Flip Flop'.
208  * After that, keep track of it. :-)
209  * --- In order to do that, the DMA routines below should ---
210  * --- only be used while interrupts are disabled! ---
220 /* set mode (above) for a specific DMA channel */
231  * the lower 16 bits of the DMA current address register, but a 64k boundary
268 /* Set transfer address & page bits for specific DMA channel.
269  * Assumes dma flipflop is clear.
289  * a specific DMA channel.
293  * Assumes dma flip-flop is clear.
294  * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
298 	count--;  in set_dma_count()
313 /* Get DMA residue count. After a DMA transfer, this
314  * should return zero. Reading this while a DMA transfer is
316  * If called before the channel has been used, it may return 1.
319  * Assumes DMA flip-flop is clear.
327 	/* using short to get 16-bit wrap around */  in get_dma_residue()
336 /* These are in kernel/dma.c: */
338 /* reserve a DMA channel */