include/asm/dma.h

1 /* SPDX-License-Identifier: GPL-2.0 */
3  * include/asm-alpha/dma.h
5  * This is essentially the same as the i386 DMA stuff, as the AlphaPCs
6  * use ISA-compatible dma.  The only extension is support for high-page
7  * registers that allow to set the top 8 bits of a 32-bit DMA address.
8  * This register should be written last when setting up a DMA address
9  * as this will also enable DMA across 64 KB boundaries.
12 /* $Id: dma.h,v 1.7 1992/12/14 00:29:34 root Exp root $
13  * linux/include/asm/dma.h: Defines for using and allocating dma channels.
15  * High DMA channel support & info by Hannu Savolainen
29  * NOTES about DMA transfers:
31  *  controller 1: channels 0-3, byte operations, ports 00-1F
32  *  controller 2: channels 4-7, word operations, ports C0-DF
34  *  - ALL registers are 8 bits only, regardless of transfer size
35  *  - channel 4 is not used - cascades 1 into 2.
36  *  - channels 0-3 are byte - addresses/counts are for physical bytes
37  *  - channels 5-7 are word - addresses/counts are for physical words
38  *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
39  *  - transfer count loaded to registers is 1 less than actual count
40  *  - controller 2 offsets are all even (2x offsets for controller 1)
41  *  - page registers for 5-7 don't use data bit 0, represent 128K pages
42  *  - page registers for 0-3 use bit 0, represent 64K pages
44  * DMA transfers are limited to the lower 16MB of _physical_ memory.
48  *  Address mapping for channels 0-3:
55  * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
57  *  Address mapping for channels 5-7:
64  * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
66  * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
67  * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
68  * the hardware level, so odd-byte transfers aren't possible).
71  * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
72  * and up to 128K bytes may be transferred on channels 5-7 in one operation.
79   ISA DMA limitations on Alpha platforms,
81   These may be due to SIO (PCI<->ISA bridge) chipset limitation, or
85 /* The maximum address for ISA DMA transfer on RUFFIAN,
90 /* The maximum address for ISA DMA transfer on SABLE, and some ALCORs,
97   Maximum address for all the others is the complete 32-bit bus
116 /* If we have the iommu, we don't have any address limitations on DMA.
117    Otherwise (Nautilus, RX164), we have to have 0-16 Mb DMA zone
122 /* 8237 DMA controllers */
123 #define IO_DMA1_BASE	0x00	/* 8 bit slave DMA, channels 0..3 */
124 #define IO_DMA2_BASE	0xC0	/* 16 bit master DMA, ch 4(=slave input)..7 */
126 /* DMA controller registers */
130 #define DMA1_MASK_REG		0x0A	/* single-channel mask (w) */
132 #define DMA1_CLEAR_FF_REG	0x0C	/* clear pointer flip-flop (w) */
135 #define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
136 #define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */
142 #define DMA2_MASK_REG		0xD4	/* single-channel mask (w) */
144 #define DMA2_CLEAR_FF_REG	0xD8	/* clear pointer flip-flop (w) */
147 #define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
148 #define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */
151 #define DMA_ADDR_0              0x00    /* DMA address registers */
160 #define DMA_CNT_0               0x01    /* DMA count registers */
169 #define DMA_PAGE_0              0x87    /* DMA page registers */
188 #define DMA_MODE_CASCADE 0xC0   /* pass thru DREQ->HRQ, DACK<-HLDA only */
206 /* enable/disable a specific DMA channel */
223 /* Clear the 'DMA Pointer Flip Flop'.
226  * After that, keep track of it. :-)
227  * --- In order to do that, the DMA routines below should ---
228  * --- only be used while interrupts are disabled! ---
238 /* set mode (above) for a specific DMA channel */
247 /* set extended mode for a specific DMA channel */
258  * the lower 16 bits of the DMA current address register.
295 /* Set transfer address & page bits for specific DMA channel.
296  * Assumes dma flipflop is clear.
307 	set_dma_page(dmanr, a>>16);	/* set hipage last to enable 32-bit mode */  in set_dma_addr()
312  * a specific DMA channel.
316  * Assumes dma flip-flop is clear.
317  * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
321         count--;  in set_dma_count()
332 /* Get DMA residue count. After a DMA transfer, this
333  * should return zero. Reading this while a DMA transfer is
335  * If called before the channel has been used, it may return 1.
338  * Assumes DMA flip-flop is clear.
345 	/* using short to get 16-bit wrap around */  in get_dma_residue()
355 /* These are in kernel/dma.c: */
356 extern int request_dma(unsigned int dmanr, const char * device_id);	/* reserve a DMA channel */