Lines Matching +full:dma +full:- +full:channel +full:- +full:mask
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Special handling for DW DMA core
9 #include <linux/dma-mapping.h>
15 #include <linux/platform_data/dma-dw.h>
19 #include "spi-dw.h"
30 if (s->dma_dev != chan->device->dev) in dw_spi_dma_chan_filter()
33 chan->private = s; in dw_spi_dma_chan_filter()
43 def_burst = dws->fifo_len / 2; in dw_spi_dma_maxburst_init()
45 ret = dma_get_slave_caps(dws->rxchan, &caps); in dw_spi_dma_maxburst_init()
51 dws->rxburst = min(max_burst, def_burst); in dw_spi_dma_maxburst_init()
52 dw_writel(dws, DW_SPI_DMARDLR, dws->rxburst - 1); in dw_spi_dma_maxburst_init()
54 ret = dma_get_slave_caps(dws->txchan, &caps); in dw_spi_dma_maxburst_init()
61 * Having a Rx DMA channel serviced with higher priority than a Tx DMA in dw_spi_dma_maxburst_init()
62 * channel might not be enough to provide a well balanced DMA-based in dw_spi_dma_maxburst_init()
63 * SPI transfer interface. There might still be moments when the Tx DMA in dw_spi_dma_maxburst_init()
64 * channel is occasionally handled faster than the Rx DMA channel. in dw_spi_dma_maxburst_init()
67 * cleared by the Rx DMA channel. In order to fix the problem the Tx in dw_spi_dma_maxburst_init()
68 * DMA activity is intentionally slowed down by limiting the SPI Tx in dw_spi_dma_maxburst_init()
71 dws->txburst = min(max_burst, def_burst); in dw_spi_dma_maxburst_init()
72 dw_writel(dws, DW_SPI_DMATDLR, dws->txburst); in dw_spi_dma_maxburst_init()
80 ret = dma_get_slave_caps(dws->txchan, &tx); in dw_spi_dma_caps_init()
84 ret = dma_get_slave_caps(dws->rxchan, &rx); in dw_spi_dma_caps_init()
90 return -ENXIO; in dw_spi_dma_caps_init()
93 dws->dma_sg_burst = min(tx.max_sg_burst, rx.max_sg_burst); in dw_spi_dma_caps_init()
95 dws->dma_sg_burst = tx.max_sg_burst; in dw_spi_dma_caps_init()
97 dws->dma_sg_burst = rx.max_sg_burst; in dw_spi_dma_caps_init()
99 dws->dma_sg_burst = 0; in dw_spi_dma_caps_init()
102 * Assuming both channels belong to the same DMA controller hence the in dw_spi_dma_caps_init()
106 dws->dma_addr_widths = tx.dst_addr_widths & rx.src_addr_widths; in dw_spi_dma_caps_init()
116 dma_cap_mask_t mask; in dw_spi_dma_init_mfld() local
117 int ret = -EBUSY; in dw_spi_dma_init_mfld()
120 * Get pci device for DMA controller, currently it could only in dw_spi_dma_init_mfld()
121 * be the DMA controller of Medfield in dw_spi_dma_init_mfld()
125 return -ENODEV; in dw_spi_dma_init_mfld()
127 dma_cap_zero(mask); in dw_spi_dma_init_mfld()
128 dma_cap_set(DMA_SLAVE, mask); in dw_spi_dma_init_mfld()
130 /* 1. Init rx channel */ in dw_spi_dma_init_mfld()
131 rx->dma_dev = &dma_dev->dev; in dw_spi_dma_init_mfld()
132 dws->rxchan = dma_request_channel(mask, dw_spi_dma_chan_filter, rx); in dw_spi_dma_init_mfld()
133 if (!dws->rxchan) in dw_spi_dma_init_mfld()
136 /* 2. Init tx channel */ in dw_spi_dma_init_mfld()
137 tx->dma_dev = &dma_dev->dev; in dw_spi_dma_init_mfld()
138 dws->txchan = dma_request_channel(mask, dw_spi_dma_chan_filter, tx); in dw_spi_dma_init_mfld()
139 if (!dws->txchan) in dw_spi_dma_init_mfld()
142 dws->host->dma_rx = dws->rxchan; in dw_spi_dma_init_mfld()
143 dws->host->dma_tx = dws->txchan; in dw_spi_dma_init_mfld()
145 init_completion(&dws->dma_completion); in dw_spi_dma_init_mfld()
158 dma_release_channel(dws->txchan); in dw_spi_dma_init_mfld()
159 dws->txchan = NULL; in dw_spi_dma_init_mfld()
161 dma_release_channel(dws->rxchan); in dw_spi_dma_init_mfld()
162 dws->rxchan = NULL; in dw_spi_dma_init_mfld()
172 dws->rxchan = dma_request_chan(dev, "rx"); in dw_spi_dma_init_generic()
173 if (IS_ERR(dws->rxchan)) { in dw_spi_dma_init_generic()
174 ret = PTR_ERR(dws->rxchan); in dw_spi_dma_init_generic()
175 dws->rxchan = NULL; in dw_spi_dma_init_generic()
179 dws->txchan = dma_request_chan(dev, "tx"); in dw_spi_dma_init_generic()
180 if (IS_ERR(dws->txchan)) { in dw_spi_dma_init_generic()
181 ret = PTR_ERR(dws->txchan); in dw_spi_dma_init_generic()
182 dws->txchan = NULL; in dw_spi_dma_init_generic()
186 dws->host->dma_rx = dws->rxchan; in dw_spi_dma_init_generic()
187 dws->host->dma_tx = dws->txchan; in dw_spi_dma_init_generic()
189 init_completion(&dws->dma_completion); in dw_spi_dma_init_generic()
200 dma_release_channel(dws->txchan); in dw_spi_dma_init_generic()
201 dws->txchan = NULL; in dw_spi_dma_init_generic()
203 dma_release_channel(dws->rxchan); in dw_spi_dma_init_generic()
204 dws->rxchan = NULL; in dw_spi_dma_init_generic()
211 if (dws->txchan) { in dw_spi_dma_exit()
212 dmaengine_terminate_sync(dws->txchan); in dw_spi_dma_exit()
213 dma_release_channel(dws->txchan); in dw_spi_dma_exit()
216 if (dws->rxchan) { in dw_spi_dma_exit()
217 dmaengine_terminate_sync(dws->rxchan); in dw_spi_dma_exit()
218 dma_release_channel(dws->rxchan); in dw_spi_dma_exit()
226 complete(&dws->dma_completion); in dw_spi_dma_transfer_handler()
251 if (xfer->len <= dws->fifo_len) in dw_spi_can_dma()
254 dma_bus_width = dw_spi_dma_convert_width(dws->n_bytes); in dw_spi_can_dma()
256 return dws->dma_addr_widths & BIT(dma_bus_width); in dw_spi_can_dma()
270 ms = wait_for_completion_timeout(&dws->dma_completion, in dw_spi_dma_wait()
274 dev_err(&dws->host->cur_msg->spi->dev, in dw_spi_dma_wait()
275 "DMA transaction timed out\n"); in dw_spi_dma_wait()
276 return -ETIMEDOUT; in dw_spi_dma_wait()
296 delay.value = nents * dws->n_bytes * BITS_PER_BYTE; in dw_spi_dma_wait_tx_done()
298 while (dw_spi_dma_tx_busy(dws) && retry--) in dw_spi_dma_wait_tx_done()
302 dev_err(&dws->host->dev, "Tx hanged up\n"); in dw_spi_dma_wait_tx_done()
303 return -EIO; in dw_spi_dma_wait_tx_done()
310 * dws->dma_chan_busy is set before the dma transfer starts, callback for tx
311 * channel will clear a corresponding bit.
317 clear_bit(DW_SPI_TX_BUSY, &dws->dma_chan_busy); in dw_spi_dma_tx_done()
318 if (test_bit(DW_SPI_RX_BUSY, &dws->dma_chan_busy)) in dw_spi_dma_tx_done()
321 complete(&dws->dma_completion); in dw_spi_dma_tx_done()
330 txconf.dst_addr = dws->dma_addr; in dw_spi_dma_config_tx()
331 txconf.dst_maxburst = dws->txburst; in dw_spi_dma_config_tx()
333 txconf.dst_addr_width = dw_spi_dma_convert_width(dws->n_bytes); in dw_spi_dma_config_tx()
336 return dmaengine_slave_config(dws->txchan, &txconf); in dw_spi_dma_config_tx()
346 txdesc = dmaengine_prep_slave_sg(dws->txchan, sgl, nents, in dw_spi_dma_submit_tx()
350 return -ENOMEM; in dw_spi_dma_submit_tx()
352 txdesc->callback = dw_spi_dma_tx_done; in dw_spi_dma_submit_tx()
353 txdesc->callback_param = dws; in dw_spi_dma_submit_tx()
358 dmaengine_terminate_sync(dws->txchan); in dw_spi_dma_submit_tx()
362 set_bit(DW_SPI_TX_BUSY, &dws->dma_chan_busy); in dw_spi_dma_submit_tx()
380 * It's unlikely that DMA engine is still doing the data fetching, but in dw_spi_dma_wait_rx_done()
389 ns = 4U * NSEC_PER_SEC / dws->max_freq * nents; in dw_spi_dma_wait_rx_done()
399 while (dw_spi_dma_rx_busy(dws) && retry--) in dw_spi_dma_wait_rx_done()
403 dev_err(&dws->host->dev, "Rx hanged up\n"); in dw_spi_dma_wait_rx_done()
404 return -EIO; in dw_spi_dma_wait_rx_done()
411 * dws->dma_chan_busy is set before the dma transfer starts, callback for rx
412 * channel will clear a corresponding bit.
418 clear_bit(DW_SPI_RX_BUSY, &dws->dma_chan_busy); in dw_spi_dma_rx_done()
419 if (test_bit(DW_SPI_TX_BUSY, &dws->dma_chan_busy)) in dw_spi_dma_rx_done()
422 complete(&dws->dma_completion); in dw_spi_dma_rx_done()
431 rxconf.src_addr = dws->dma_addr; in dw_spi_dma_config_rx()
432 rxconf.src_maxburst = dws->rxburst; in dw_spi_dma_config_rx()
434 rxconf.src_addr_width = dw_spi_dma_convert_width(dws->n_bytes); in dw_spi_dma_config_rx()
437 return dmaengine_slave_config(dws->rxchan, &rxconf); in dw_spi_dma_config_rx()
447 rxdesc = dmaengine_prep_slave_sg(dws->rxchan, sgl, nents, in dw_spi_dma_submit_rx()
451 return -ENOMEM; in dw_spi_dma_submit_rx()
453 rxdesc->callback = dw_spi_dma_rx_done; in dw_spi_dma_submit_rx()
454 rxdesc->callback_param = dws; in dw_spi_dma_submit_rx()
459 dmaengine_terminate_sync(dws->rxchan); in dw_spi_dma_submit_rx()
463 set_bit(DW_SPI_RX_BUSY, &dws->dma_chan_busy); in dw_spi_dma_submit_rx()
473 if (!xfer->tx_buf) in dw_spi_dma_setup()
474 return -EINVAL; in dw_spi_dma_setup()
476 /* Setup DMA channels */ in dw_spi_dma_setup()
481 if (xfer->rx_buf) { in dw_spi_dma_setup()
487 /* Set the DMA handshaking interface */ in dw_spi_dma_setup()
489 if (xfer->rx_buf) in dw_spi_dma_setup()
493 /* Set the interrupt mask */ in dw_spi_dma_setup()
495 if (xfer->rx_buf) in dw_spi_dma_setup()
499 reinit_completion(&dws->dma_completion); in dw_spi_dma_setup()
501 dws->transfer_handler = dw_spi_dma_transfer_handler; in dw_spi_dma_setup()
511 /* Submit the DMA Tx transfer */ in dw_spi_dma_transfer_all()
512 ret = dw_spi_dma_submit_tx(dws, xfer->tx_sg.sgl, xfer->tx_sg.nents); in dw_spi_dma_transfer_all()
516 /* Submit the DMA Rx transfer if required */ in dw_spi_dma_transfer_all()
517 if (xfer->rx_buf) { in dw_spi_dma_transfer_all()
518 ret = dw_spi_dma_submit_rx(dws, xfer->rx_sg.sgl, in dw_spi_dma_transfer_all()
519 xfer->rx_sg.nents); in dw_spi_dma_transfer_all()
524 dma_async_issue_pending(dws->rxchan); in dw_spi_dma_transfer_all()
527 dma_async_issue_pending(dws->txchan); in dw_spi_dma_transfer_all()
529 ret = dw_spi_dma_wait(dws, xfer->len, xfer->effective_speed_hz); in dw_spi_dma_transfer_all()
538 * In case if at least one of the requested DMA channels doesn't support the
539 * hardware accelerated SG list entries traverse, the DMA driver will most
540 * likely work that around by performing the IRQ-based SG list entries
541 * resubmission. That might and will cause a problem if the DMA Tx channel is
542 * recharged and re-executed before the Rx DMA channel. Due to
543 * non-deterministic IRQ-handler execution latency the DMA Tx channel will
544 * start pushing data to the SPI bus before the Rx DMA channel is even
545 * reinitialized with the next inbound SG list entry. By doing so the DMA Tx
546 * channel will implicitly start filling the DW APB SSI Rx FIFO up, which while
547 * the DMA Rx channel being recharged and re-executed will eventually be
550 * In order to solve the problem we have to feed the DMA engine with SG list
551 * entries one-by-one. It shall keep the DW APB SSI Tx and Rx FIFOs
554 * (though total length should match) let's virtually split the SG-lists to the
555 * set of DMA transfers, which length is a minimum of the ordered SG-entries
556 * lengths. An ASCII-sketch of the implemented algo is following:
557 * xfer->len
561 * DMA transfers: |_|_|__|_|__|
563 * Note in order to have this workaround solving the denoted problem the DMA
565 * the DMA device max segment size parameter with maximum data block size the
566 * DMA engine supports.
580 for (base = 0; base < xfer->len; base += len) { in dw_spi_dma_transfer_one()
581 /* Fetch next Tx DMA data chunk */ in dw_spi_dma_transfer_one()
583 tx_sg = !tx_sg ? &xfer->tx_sg.sgl[0] : sg_next(tx_sg); in dw_spi_dma_transfer_one()
588 /* Fetch next Rx DMA data chunk */ in dw_spi_dma_transfer_one()
590 rx_sg = !rx_sg ? &xfer->rx_sg.sgl[0] : sg_next(rx_sg); in dw_spi_dma_transfer_one()
600 /* Submit DMA Tx transfer */ in dw_spi_dma_transfer_one()
605 /* Submit DMA Rx transfer */ in dw_spi_dma_transfer_one()
611 dma_async_issue_pending(dws->rxchan); in dw_spi_dma_transfer_one()
613 dma_async_issue_pending(dws->txchan); in dw_spi_dma_transfer_one()
616 * Here we only need to wait for the DMA transfer to be in dw_spi_dma_transfer_one()
621 ret = dw_spi_dma_wait(dws, len, xfer->effective_speed_hz); in dw_spi_dma_transfer_one()
625 reinit_completion(&dws->dma_completion); in dw_spi_dma_transfer_one()
629 tx_len -= len; in dw_spi_dma_transfer_one()
630 rx_len -= len; in dw_spi_dma_transfer_one()
643 nents = max(xfer->tx_sg.nents, xfer->rx_sg.nents); in dw_spi_dma_transfer()
646 * Execute normal DMA-based transfer (which submits the Rx and Tx SG in dw_spi_dma_transfer()
647 * lists directly to the DMA engine at once) if either full hardware in dw_spi_dma_transfer()
649 * Tx-only SPI transfer is requested, or the DMA engine is capable to in dw_spi_dma_transfer()
652 if (!dws->dma_sg_burst || !xfer->rx_buf || nents <= dws->dma_sg_burst) in dw_spi_dma_transfer()
659 if (dws->host->cur_msg->status == -EINPROGRESS) { in dw_spi_dma_transfer()
665 if (xfer->rx_buf && dws->host->cur_msg->status == -EINPROGRESS) in dw_spi_dma_transfer()
673 if (test_bit(DW_SPI_TX_BUSY, &dws->dma_chan_busy)) { in dw_spi_dma_stop()
674 dmaengine_terminate_sync(dws->txchan); in dw_spi_dma_stop()
675 clear_bit(DW_SPI_TX_BUSY, &dws->dma_chan_busy); in dw_spi_dma_stop()
677 if (test_bit(DW_SPI_RX_BUSY, &dws->dma_chan_busy)) { in dw_spi_dma_stop()
678 dmaengine_terminate_sync(dws->rxchan); in dw_spi_dma_stop()
679 clear_bit(DW_SPI_RX_BUSY, &dws->dma_chan_busy); in dw_spi_dma_stop()
694 dws->dma_ops = &dw_spi_dma_mfld_ops; in dw_spi_dma_setup_mfld()
709 dws->dma_ops = &dw_spi_dma_generic_ops; in dw_spi_dma_setup_generic()