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/linux-6.12.1/drivers/mtd/maps/
Dphysmap-bt1-rom.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Baikal-T1 Physically Mapped Internal ROM driver
21 #include "physmap-bt1-rom.h"
24 * Baikal-T1 SoC ROMs are only accessible by the dword-aligned instructions.
25 * We have to take this into account when implementing the data read-methods.
26 * Note there is no need in bothering with endianness, since both Baikal-T1
32 void __iomem *src = map->virt + ofs; in bt1_rom_map_read()
33 unsigned int shift; in bt1_rom_map_read() local
35 u32 data; in bt1_rom_map_read() local
37 /* Read data within offset dword. */ in bt1_rom_map_read()
[all …]
/linux-6.12.1/drivers/clk/meson/
Ds4-pll.c1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
5 * Copyright (c) 2022-2023 Amlogic, inc. All rights reserved
9 #include <linux/clk-provider.h>
13 #include "clk-mpll.h"
14 #include "clk-pll.h"
15 #include "clk-regmap.h"
16 #include "s4-pll.h"
17 #include "meson-clkc-utils.h"
18 #include <dt-bindings/clock/amlogic,s4-pll-clkc.h>
25 * in the kernel phase. Write of fixed PLL-related register will cause the system to crash.
[all …]
Daxg.c1 // SPDX-License-Identifier: GPL-2.0+
3 * AmLogic Meson-AXG Clock Controller Driver
12 #include <linux/clk-provider.h>
18 #include "clk-regmap.h"
19 #include "clk-pll.h"
20 #include "clk-mpll.h"
22 #include "meson-eeclk.h"
24 #include <dt-bindings/clock/axg-clkc.h>
29 .data = &(struct meson_clk_pll_data){
32 .shift = 30,
[all …]
Ds4-peripherals.c1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
5 * Copyright (c) 2022-2023 Amlogic, inc. All rights reserved
9 #include <linux/clk-provider.h>
13 #include "clk-regmap.h"
14 #include "vid-pll-div.h"
15 #include "clk-dualdiv.h"
16 #include "s4-peripherals.h"
17 #include "meson-clkc-utils.h"
18 #include <dt-bindings/clock/amlogic,s4-peripherals-clkc.h>
21 .data = &(struct clk_regmap_gate_data){
[all …]
Da1-peripherals.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/clk-provider.h>
13 #include "a1-peripherals.h"
14 #include "clk-dualdiv.h"
15 #include "clk-regmap.h"
16 #include "meson-clkc-utils.h"
18 #include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
21 .data = &(struct clk_regmap_gate_data){
36 .data = &(struct clk_regmap_gate_data){
51 .data = &(struct clk_regmap_gate_data){
[all …]
Dgxbb.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
14 #include "clk-regmap.h"
15 #include "clk-pll.h"
16 #include "clk-mpll.h"
17 #include "meson-eeclk.h"
18 #include "vid-pll-div.h"
20 #include <dt-bindings/clock/gxbb-clkc.h>
89 .data = &(struct meson_clk_pll_data){
92 .shift = 30,
[all …]
Dg12a.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Amlogic Meson-G12A Clock Controller Driver
13 #include <linux/clk-provider.h>
20 #include "clk-mpll.h"
21 #include "clk-pll.h"
22 #include "clk-regmap.h"
23 #include "clk-cpu-dyndiv.h"
24 #include "vid-pll-div.h"
26 #include "meson-eeclk.h"
29 #include <dt-bindings/clock/g12a-clkc.h>
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Dc3-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
11 #include "clk-regmap.h"
12 #include "clk-pll.h"
13 #include "meson-clkc-utils.h"
14 #include <dt-bindings/clock/amlogic,c3-pll-clkc.h>
38 .data = &(struct clk_regmap_gate_data) {
79 .data = &(struct clk_regmap_gate_data) {
107 .data = &(struct clk_regmap_gate_data) {
135 .data = &(struct clk_regmap_gate_data) {
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Dg12a-aoclk.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Amlogic Meson-AXG Clock Controller Driver
11 #include <linux/clk-provider.h>
13 #include <linux/reset-controller.h>
16 #include "meson-aoclk.h"
18 #include "clk-regmap.h"
19 #include "clk-dualdiv.h"
21 #include <dt-bindings/clock/g12a-aoclkc.h>
22 #include <dt-bindings/reset/g12a-aoclkc.h>
26 * Register offsets from the data sheet must be multiplied by 4.
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Dc3-peripherals.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
11 #include "clk-regmap.h"
12 #include "clk-dualdiv.h"
13 #include "meson-clkc-utils.h"
14 #include <dt-bindings/clock/amlogic,c3-peripherals-clkc.h>
52 .data = &(struct clk_regmap_gate_data) {
72 .data = &(struct meson_clk_dualdiv_data) {
75 .shift = 0,
80 .shift = 12,
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/linux-6.12.1/arch/arm64/lib/
Dcsum.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2019-2020 Arm Ltd.
5 #include <linux/kasan-checks.h>
10 /* Looks dumb, but generates nice-ish code */
11 static u64 accumulate(u64 sum, u64 data) in accumulate() argument
13 __uint128_t tmp = (__uint128_t)sum + data; in accumulate()
18 * We over-read the buffer and this makes KASAN unhappy. Instead, disable
23 unsigned int offset, shift, sum; in do_csum() local
25 u64 data, sum64 = 0; in do_csum() local
34 * should absolutely not be pointing to anything read-sensitive. We do, in do_csum()
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/linux-6.12.1/arch/sh/drivers/pci/
Dops-sh4.c1 // SPDX-License-Identifier: GPL-2.0
3 * Generic SH-4 / SH-4A PCIC operations (SH7751, SH7780).
5 * Copyright (C) 2002 - 2009 Paul Mundt
11 #include "pci-sh4.h"
17 (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
25 struct pci_channel *chan = bus->sysdata; in sh4_pci_read()
27 u32 data; in sh4_pci_read() local
35 data = pci_read_reg(chan, SH4_PCIPDR); in sh4_pci_read()
40 *val = (data >> ((where & 3) << 3)) & 0xff; in sh4_pci_read()
43 *val = (data >> ((where & 2) << 3)) & 0xffff; in sh4_pci_read()
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/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/
Dnv50.c29 struct nvkm_device *device = gpio->subdev.device; in nv50_gpio_reset()
30 struct nvkm_bios *bios = device->bios; in nv50_gpio_reset()
33 int ent = -1; in nv50_gpio_reset()
37 u32 data = nvbios_rd32(bios, entry); in nv50_gpio_reset() local
38 u8 line = (data & 0x0000001f); in nv50_gpio_reset()
39 u8 func = (data & 0x0000ff00) >> 8; in nv50_gpio_reset()
40 u8 defs = !!(data & 0x01000000); in nv50_gpio_reset()
41 u8 unk0 = !!(data & 0x02000000); in nv50_gpio_reset()
42 u8 unk1 = !!(data & 0x04000000); in nv50_gpio_reset()
58 nv50_gpio_location(int line, u32 *reg, u32 *shift) in nv50_gpio_location() argument
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/linux-6.12.1/sound/soc/sprd/
Dsprd-mcdt.c1 // SPDX-License-Identifier: GPL-2.0
14 #include "sprd-mcdt.h"
121 u32 orig = readl_relaxed(mcdt->base + reg); in sprd_mcdt_update()
125 writel_relaxed(tmp, mcdt->base + reg); in sprd_mcdt_update()
155 u32 shift = MCDT_DAC_DMA_SHIFT + channel; in sprd_mcdt_dac_dma_enable() local
158 sprd_mcdt_update(mcdt, MCDT_DMA_EN, BIT(shift), BIT(shift)); in sprd_mcdt_dac_dma_enable()
160 sprd_mcdt_update(mcdt, MCDT_DMA_EN, 0, BIT(shift)); in sprd_mcdt_dac_dma_enable()
187 writel_relaxed(val, mcdt->base + reg); in sprd_mcdt_dac_write_fifo()
195 *val = readl_relaxed(mcdt->base + reg); in sprd_mcdt_adc_read_fifo()
298 u32 reg, shift = sprd_mcdt_dma_ack_shift(channel), ack = dma_chan; in sprd_mcdt_dac_dma_ack_select() local
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/linux-6.12.1/drivers/pinctrl/samsung/
Dpinctrl-s3c64xx.c1 // SPDX-License-Identifier: GPL-2.0+
3 // S3C64xx specific support for pinctrl-samsung driver.
7 // Based on pinctrl-exynos.c, please see the file for original copyrights.
24 #include "pinctrl-samsung.h"
116 .eint_mask = (1 << (pins)) - 1, \
140 .eint_mask = (1 << (pins)) - 1, \
194 .eint_mask = (1 << (pins)) - 1, \
200 * struct s3c64xx_eint0_data - EINT0 common data
201 * @drvdata: pin controller driver data
212 * struct s3c64xx_eint0_domain_data - EINT0 per-domain data
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/linux-6.12.1/kernel/time/
Dvsyscall.c1 // SPDX-License-Identifier: GPL-2.0
24 vdata[CS_HRES_COARSE].cycle_last = tk->tkr_mono.cycle_last; in update_vdso_data()
26 vdata[CS_HRES_COARSE].max_cycles = tk->tkr_mono.clock->max_cycles; in update_vdso_data()
28 vdata[CS_HRES_COARSE].mask = tk->tkr_mono.mask; in update_vdso_data()
29 vdata[CS_HRES_COARSE].mult = tk->tkr_mono.mult; in update_vdso_data()
30 vdata[CS_HRES_COARSE].shift = tk->tkr_mono.shift; in update_vdso_data()
31 vdata[CS_RAW].cycle_last = tk->tkr_raw.cycle_last; in update_vdso_data()
33 vdata[CS_RAW].max_cycles = tk->tkr_raw.clock->max_cycles; in update_vdso_data()
35 vdata[CS_RAW].mask = tk->tkr_raw.mask; in update_vdso_data()
36 vdata[CS_RAW].mult = tk->tkr_raw.mult; in update_vdso_data()
[all …]
/linux-6.12.1/sound/pci/emu10k1/
Demu10k1_patch.c1 // SPDX-License-Identifier: GPL-2.0-or-later
22 * allocate a sample block and copy data from userspace
27 const void __user *data, long count) in snd_emu10k1_sample_new() argument
31 int shift; in snd_emu10k1_sample_new() local
37 emu = rec->hw; in snd_emu10k1_sample_new()
39 return -EINVAL; in snd_emu10k1_sample_new()
41 if (sp->v.mode_flags & (SNDRV_SFNT_SAMPLE_BIDIR_LOOP | SNDRV_SFNT_SAMPLE_REVERSE_LOOP)) { in snd_emu10k1_sample_new()
42 /* should instead return -ENOTSUPP; but compatibility */ in snd_emu10k1_sample_new()
43 dev_warn(emu->card->dev, in snd_emu10k1_sample_new()
45 sp->v.sample); in snd_emu10k1_sample_new()
[all …]
/linux-6.12.1/arch/arm/mach-omap2/
Dvc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
22 * struct omap_vc_common - per-VC register/bitfield data
26 * @data_shift: DATA field shift in PRM_VC_BYPASS_VAL register
27 * @slaveaddr_shift: SLAVEADDR field shift in PRM_VC_BYPASS_VAL register
28 * @regaddr_shift: REGADDR field shift in PRM_VC_BYPASS_VAL register
29 * @cmd_on_shift: ON field shift in PRM_VC_CMD_VAL_* register
30 * @cmd_onlp_shift: ONLP field shift in PRM_VC_CMD_VAL_* register
31 * @cmd_ret_shift: RET field shift in PRM_VC_CMD_VAL_* register
32 * @cmd_off_shift: OFF field shift in PRM_VC_CMD_VAL_* register
34 * @i2c_cfg_clear_mask: high-speed mode bit clear mask in I2C config register
[all …]
/linux-6.12.1/drivers/clk/hisilicon/
Dclkdivider-hi6220.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
19 #define div_mask(width) ((1 << (width)) - 1)
22 * struct hi6220_clk_divider - divider clock for hi6220
24 * @hw: handle between common and hardware-specific interfaces
26 * @shift: shift to the divider bit field
35 u8 shift; member
51 val = readl_relaxed(dclk->reg) >> dclk->shift; in hi6220_clkdiv_recalc_rate()
52 val &= div_mask(dclk->width); in hi6220_clkdiv_recalc_rate()
54 return divider_recalc_rate(hw, parent_rate, val, dclk->table, in hi6220_clkdiv_recalc_rate()
[all …]
/linux-6.12.1/arch/riscv/lib/
Dcsum.c1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2023-2024 Rivos Inc.
11 #include <linux/kasan-checks.h>
27 sum += (__force unsigned long)saddr->s6_addr32[0]; in csum_ipv6_magic()
28 sum += (__force unsigned long)saddr->s6_addr32[1]; in csum_ipv6_magic()
29 sum += (__force unsigned long)saddr->s6_addr32[2]; in csum_ipv6_magic()
30 sum += (__force unsigned long)saddr->s6_addr32[3]; in csum_ipv6_magic()
32 sum += (__force unsigned long)daddr->s6_addr32[0]; in csum_ipv6_magic()
33 sum += (__force unsigned long)daddr->s6_addr32[1]; in csum_ipv6_magic()
34 sum += (__force unsigned long)daddr->s6_addr32[2]; in csum_ipv6_magic()
[all …]
/linux-6.12.1/drivers/media/pci/netup_unidvb/
Dnetup_unidvb_ci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * DVB CAM support for NetUP Universal Dual DVB-CI
43 /* BIT_CAM_BYPASS bit shift for SLOT 1 */
48 writew(0x101, ndev->bmmio0 + CAM_CTRLSTAT_CLR); in netup_ci_interrupt()
55 struct netup_ci_state *state = en50221->data; in netup_unidvb_ci_slot_ts_ctl()
56 struct netup_unidvb_dev *dev = state->dev; in netup_unidvb_ci_slot_ts_ctl()
57 u16 shift = (state->nr == 1) ? CAM1_SHIFT : 0; in netup_unidvb_ci_slot_ts_ctl() local
59 dev_dbg(&dev->pci_dev->dev, "%s(): CAM_CTRLSTAT=0x%x\n", in netup_unidvb_ci_slot_ts_ctl()
60 __func__, readw(dev->bmmio0 + CAM_CTRLSTAT_READ_SET)); in netup_unidvb_ci_slot_ts_ctl()
62 return -EINVAL; in netup_unidvb_ci_slot_ts_ctl()
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/linux-6.12.1/arch/mips/cavium-octeon/executive/
Dcvmx-helper-jtag.c8 * Copyright (c) 2003-2008 Cavium Networks
15 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
36 #include <asm/octeon/cvmx-helper-jtag.h>
50 uint32_t divisor = cvmx_sysinfo_get()->cpu_clock_hz / (25 * 1000000); in cvmx_helper_qlm_jtag_init()
51 divisor = (divisor - 1) >> 2; in cvmx_helper_qlm_jtag_init()
52 /* Convert the divisor into a power of 2 shift */ in cvmx_helper_qlm_jtag_init()
75 * into the MSB and out the LSB, so you should shift in the low
79 * @qlm: QLM to shift value into
80 * @bits: Number of bits to shift in (1-32).
[all …]
/linux-6.12.1/sound/soc/codecs/
Dpcm6240.c1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright (C) 2022 - 2024 Texas Instruments Incorporated
12 // Author: Shenghao Ding <shenghao-ding@ti.com>
63 .shift = 1,
69 .shift = 1,
78 .shift = 0,
84 .shift = 0,
93 .shift = 0,
99 .shift = 0,
105 .shift = 0,
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/linux-6.12.1/drivers/mfd/
Datmel-smc.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
11 #include <linux/mfd/syscon/atmel-smc.h>
15 * atmel_smc_cs_conf_init - initialize a SMC CS conf
27 * atmel_smc_cs_encode_ncycles - encode a number of MCK clk cycles in the
40 * If the @ncycles value is too big to be encoded, -ERANGE is returned and
49 unsigned int lsbmask = GENMASK(msbpos - 1, 0); in atmel_smc_cs_encode_ncycles()
50 unsigned int msbmask = GENMASK(msbwidth - 1, 0); in atmel_smc_cs_encode_ncycles()
65 * We still return -ERANGE in case the caller cares. in atmel_smc_cs_encode_ncycles()
70 ret = -ERANGE; in atmel_smc_cs_encode_ncycles()
[all …]
/linux-6.12.1/include/linux/
Dclk-provider.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
14 * top-level framework. custom flags for dealing with hardware specifics
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
31 /* parents need enable during gate/ungate, set rate and re-parent */
42 * struct clk_rate_request - Structure encoding the clk constraints that
77 * struct clk_duty - Structure encoding the duty cycle ratio of a clock
88 * struct clk_ops - Callback operations for hardware clocks; these are to
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