clk/meson/g12a-aoclk.c

1 // SPDX-License-Identifier: GPL-2.0+
3  * Amlogic Meson-AXG Clock Controller Driver
11 #include <linux/clk-provider.h>
13 #include <linux/reset-controller.h>
16 #include "meson-aoclk.h"
18 #include "clk-regmap.h"
19 #include "clk-dualdiv.h"
21 #include <dt-bindings/clock/g12a-aoclkc.h>
22 #include <dt-bindings/reset/g12a-aoclkc.h>
26  * Register offsets from the data sheet must be multiplied by 4.
48 	.data = &(struct clk_regmap_gate_data) {			\
56 			.fw_name = "mpeg-clk",				\
80 	.data = &(struct clk_regmap_gate_data){
107 	.data = &(struct clk_regmap_gate_data){
122 	.data = &(struct meson_clk_dualdiv_data){
125 			.shift   = 0,
130 			.shift   = 12,
135 			.shift   = 0,
140 			.shift   = 12,
145 			.shift   = 28,
161 	.data = &(struct clk_regmap_mux_data) {
164 		.shift = 24,
180 	.data = &(struct clk_regmap_gate_data){
198 	.data = &(struct clk_regmap_gate_data){
213 	.data = &(struct meson_clk_dualdiv_data){
216 			.shift   = 0,
221 			.shift   = 12,
226 			.shift   = 0,
231 			.shift   = 12,
236 			.shift   = 28,
252 	.data = &(struct clk_regmap_mux_data) {
255 		.shift = 24,
271 	.data = &(struct clk_regmap_gate_data){
287 	.data = &(struct clk_regmap_mux_data) {
290 		.shift = 10,
298 			{ .fw_name = "ext-32k-0", },
306 	.data = &(struct clk_regmap_mux_data) {
309 		.shift = 8,
316 			{ .fw_name = "mpeg-clk", },
325 	.data = &(struct clk_regmap_mux_data) {
328 		.shift = 9,
342 	.data = &(struct clk_regmap_div_data) {
344 		.shift = 0,
359 	.data = &(struct clk_regmap_gate_data) {
462 		.compatible	= "amlogic,meson-g12a-aoclkc",
463 		.data		= &g12a_aoclkc_data,
472 		.name	= "g12a-aoclkc",
478 MODULE_DESCRIPTION("Amlogic G12A Always-ON Clock Controller driver");