Lines Matching +full:data +full:- +full:shift
1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
14 #include "clk-regmap.h"
15 #include "clk-pll.h"
16 #include "clk-mpll.h"
17 #include "meson-eeclk.h"
18 #include "vid-pll-div.h"
20 #include <dt-bindings/clock/gxbb-clkc.h>
89 .data = &(struct meson_clk_pll_data){
92 .shift = 30,
97 .shift = 0,
102 .shift = 9,
107 .shift = 0,
112 .shift = 31,
117 .shift = 29,
132 .data = &(struct clk_regmap_div_data){
134 .shift = 16,
166 .data = &(struct meson_clk_pll_data){
169 .shift = 30,
174 .shift = 0,
179 .shift = 9,
184 .shift = 0,
189 .shift = 31,
194 .shift = 28,
214 .data = &(struct meson_clk_pll_data){
217 .shift = 30,
222 .shift = 0,
227 .shift = 9,
231 * On gxl, there is a register shift due to
238 .shift = 0,
243 .shift = 31,
248 .shift = 28,
268 .data = &(struct clk_regmap_div_data){
270 .shift = 16,
286 .data = &(struct clk_regmap_div_data){
288 .shift = 22,
304 .data = &(struct clk_regmap_div_data){
306 .shift = 18,
322 .data = &(struct clk_regmap_div_data){
324 .shift = 21,
340 .data = &(struct clk_regmap_div_data){
342 .shift = 23,
358 .data = &(struct clk_regmap_div_data){
360 .shift = 19,
376 .data = &(struct meson_clk_pll_data){
379 .shift = 30,
384 .shift = 0,
389 .shift = 9,
394 .shift = 31,
399 .shift = 29,
414 .data = &(struct clk_regmap_div_data){
416 .shift = 10,
438 .data = &(struct meson_clk_pll_data){
441 .shift = 30,
446 .shift = 0,
451 .shift = 9,
456 .shift = 31,
461 .shift = 29,
487 .data = &(struct meson_clk_pll_data){
490 .shift = 30,
495 .shift = 0,
500 .shift = 9,
505 .shift = 0,
510 .shift = 31,
515 .shift = 29,
533 .data = &(struct clk_regmap_div_data){
535 .shift = 16,
551 .index = -1,
572 .data = &(struct clk_regmap_gate_data){
599 .data = &(struct clk_regmap_gate_data){
618 * b) CCF has a clock hand-off mechanism to make the sure the
637 .data = &(struct clk_regmap_gate_data){
663 .data = &(struct clk_regmap_gate_data){
689 .data = &(struct clk_regmap_gate_data){
704 .data = &(struct clk_regmap_div_data){
706 .shift = 12,
718 .data = &(struct meson_clk_mpll_data){
721 .shift = 0,
726 .shift = 25,
731 .shift = 16,
747 .data = &(struct meson_clk_mpll_data){
750 .shift = 0,
755 .shift = 15,
760 .shift = 16,
776 .data = &(struct clk_regmap_gate_data){
791 .index = -1,
799 .data = &(struct meson_clk_mpll_data){
802 .shift = 0,
807 .shift = 15,
812 .shift = 16,
828 .data = &(struct clk_regmap_gate_data){
842 .data = &(struct meson_clk_mpll_data){
845 .shift = 0,
850 .shift = 15,
855 .shift = 16,
871 .data = &(struct clk_regmap_gate_data){
896 .data = &(struct clk_regmap_mux_data){
899 .shift = 12,
916 .data = &(struct clk_regmap_div_data){
918 .shift = 0,
933 .data = &(struct clk_regmap_gate_data){
949 .data = &(struct clk_regmap_mux_data){
952 .shift = 9,
967 .data = &(struct clk_regmap_div_data){
969 .shift = 0,
984 .data = &(struct clk_regmap_gate_data){
1001 * muxed by a glitch-free switch. The CCF can manage this glitch-free
1002 * mux because it does top-to-bottom updates the each clock tree and
1018 .data = &(struct clk_regmap_mux_data){
1021 .shift = 9,
1039 .data = &(struct clk_regmap_div_data){
1041 .shift = 0,
1056 .data = &(struct clk_regmap_gate_data){
1072 .data = &(struct clk_regmap_mux_data){
1075 .shift = 25,
1093 .data = &(struct clk_regmap_div_data){
1095 .shift = 16,
1110 .data = &(struct clk_regmap_gate_data){
1131 .data = &(struct clk_regmap_mux_data){
1134 .shift = 31,
1146 .data = &(struct clk_regmap_mux_data){
1149 .shift = 9,
1166 .data = &(struct clk_regmap_div_data) {
1168 .shift = 0,
1184 .data = &(struct clk_regmap_gate_data){
1200 .data = &(struct clk_regmap_mux_data){
1203 .shift = 25,
1220 .data = &(struct clk_regmap_div_data){
1222 .shift = 16,
1238 .data = &(struct clk_regmap_gate_data){
1254 .data = &(struct clk_regmap_mux_data){
1257 .shift = 27,
1268 *The parent is specific to origin of the audio data. Let the
1282 { .name = "cts_slow_oscin", .index = -1 },
1288 .data = &(struct clk_regmap_mux_data){
1291 .shift = 16,
1303 .data = &(struct clk_regmap_div_data){
1305 .shift = 0,
1320 .data = &(struct clk_regmap_gate_data){
1351 .data = &(struct clk_regmap_mux_data){
1354 .shift = 9,
1366 .data = &(struct clk_regmap_div_data){
1368 .shift = 0,
1384 .data = &(struct clk_regmap_gate_data){
1401 .data = &(struct clk_regmap_mux_data){
1404 .shift = 25,
1416 .data = &(struct clk_regmap_div_data){
1418 .shift = 16,
1434 .data = &(struct clk_regmap_gate_data){
1451 .data = &(struct clk_regmap_mux_data){
1454 .shift = 9,
1466 .data = &(struct clk_regmap_div_data){
1468 .shift = 0,
1484 .data = &(struct clk_regmap_gate_data){
1509 .data = &(struct clk_regmap_mux_data){
1512 .shift = 9,
1528 .data = &(struct clk_regmap_div_data){
1530 .shift = 0,
1543 .data = &(struct clk_regmap_gate_data){
1557 .data = &(struct clk_regmap_mux_data){
1560 .shift = 25,
1576 .data = &(struct clk_regmap_div_data){
1578 .shift = 16,
1591 .data = &(struct clk_regmap_gate_data){
1605 .data = &(struct clk_regmap_mux_data){
1608 .shift = 31,
1636 .data = &(struct clk_regmap_mux_data){
1639 .shift = 9,
1655 .data = &(struct clk_regmap_div_data){
1657 .shift = 0,
1672 .data = &(struct clk_regmap_gate_data){
1688 .data = &(struct clk_regmap_mux_data){
1691 .shift = 25,
1707 .data = &(struct clk_regmap_div_data){
1709 .shift = 16,
1724 .data = &(struct clk_regmap_gate_data){
1740 .data = &(struct clk_regmap_mux_data){
1743 .shift = 31,
1762 .data = &(struct clk_regmap_gate_data){
1778 .data = &(struct meson_vid_pll_div_data){
1781 .shift = 0,
1786 .shift = 16,
1802 .index = -1,
1818 { .name = "hdmi_pll", .index = -1 },
1822 .data = &(struct clk_regmap_mux_data){
1825 .shift = 18,
1841 .data = &(struct clk_regmap_gate_data){
1867 .data = &(struct clk_regmap_mux_data){
1870 .shift = 16,
1887 .data = &(struct clk_regmap_mux_data){
1890 .shift = 16,
1907 .data = &(struct clk_regmap_gate_data){
1921 .data = &(struct clk_regmap_gate_data){
1935 .data = &(struct clk_regmap_div_data){
1937 .shift = 0,
1952 .data = &(struct clk_regmap_div_data){
1954 .shift = 0,
1969 .data = &(struct clk_regmap_gate_data){
1983 .data = &(struct clk_regmap_gate_data){
1997 .data = &(struct clk_regmap_gate_data){
2011 .data = &(struct clk_regmap_gate_data){
2025 .data = &(struct clk_regmap_gate_data){
2039 .data = &(struct clk_regmap_gate_data){
2053 .data = &(struct clk_regmap_gate_data){
2067 .data = &(struct clk_regmap_gate_data){
2081 .data = &(struct clk_regmap_gate_data){
2095 .data = &(struct clk_regmap_gate_data){
2109 .data = &(struct clk_regmap_gate_data){
2123 .data = &(struct clk_regmap_gate_data){
2255 .data = &(struct clk_regmap_mux_data){
2258 .shift = 28,
2271 .data = &(struct clk_regmap_mux_data){
2274 .shift = 20,
2287 .data = &(struct clk_regmap_mux_data){
2290 .shift = 28,
2318 .data = &(struct clk_regmap_mux_data){
2321 .shift = 16,
2340 .data = &(struct clk_regmap_gate_data){
2356 .data = &(struct clk_regmap_gate_data){
2372 .data = &(struct clk_regmap_gate_data){
2388 .data = &(struct clk_regmap_gate_data){
2413 .data = &(struct clk_regmap_mux_data){
2416 .shift = 9,
2429 .data = &(struct clk_regmap_div_data){
2431 .shift = 0,
2444 .data = &(struct clk_regmap_gate_data){
2467 .data = &(struct clk_regmap_mux_data){
2470 .shift = 9,
2483 .data = &(struct clk_regmap_div_data){
2485 .shift = 0,
2501 .data = &(struct clk_regmap_gate_data){
2517 .data = &(struct clk_regmap_mux_data){
2520 .shift = 25,
2533 .data = &(struct clk_regmap_div_data){
2535 .shift = 16,
2551 .data = &(struct clk_regmap_gate_data){
2583 .data = &(struct clk_regmap_mux_data){
2586 .shift = 12,
2604 .data = &(struct clk_regmap_div_data){
2606 .shift = 0,
2621 .data = &(struct clk_regmap_gate_data){
3557 { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data },
3558 { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data },
3566 .name = "gxbb-clkc",