1 /* SPDX-License-Identifier: GPL-2.0 */
3  *  Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4  *  Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
14  * top-level framework.  custom flags for dealing with hardware specifics
20 #define CLK_SET_PARENT_GATE	BIT(1) /* must be gated across re-parent */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
31 /* parents need enable during gate/ungate, set rate and re-parent */
42  * struct clk_rate_request - Structure encoding the clk constraints that
77  * struct clk_duty - Structure encoding the duty cycle ratio of a clock
88  * struct clk_ops -  Callback operations for hardware clocks; these are to
136  *		0. Returns the calculated rate. Optional, but recommended - if
152  *		Returns 0 on success, -EERROR otherwise.
168  *		Returns 0 on success, -EERROR otherwise.
179  *		Returns 0 on success, -EERROR otherwise.
184  *		Returns the calculated accuracy.  Optional - if	this op is not
189  *		Returned values are 0-359 degrees on success, negative
192  * @set_phase:	Shift the phase this clock signal in degrees specified
194  *		0-359. Return 0 on success, otherwise -EERROR.
203  *              and >= numerator) Return 0 on success, otherwise -EERROR.
205  * @init:	Perform platform-specific initialization magic.
212  *		Returns 0 on success, -EERROR otherwise.
216  * @debug_init:	Set up type-specific debugfs entries for this clock.  This
220  *		prepare_lock held.  Returns 0 on success, -EERROR otherwise.
272  * struct clk_parent_data - clk parent information
286  * struct clk_init_data - holds init data that's common to all clocks and is
292  * @parent_data: array of parent data for all possible parents (when some
297  * @flags: framework-level hints and quirks
311  * struct clk_hw - handle for traversing from a struct clk to its corresponding
312  * hardware-specific structure.  struct clk_hw should be declared within struct
319  * @clk: pointer to the per-user struct clk instance that can be used to call
322  * @init: pointer to struct clk_init_data that contains the init data shared
342  * struct clk_fixed_rate - fixed-rate clock
343  * @hw:		handle between common and hardware-specific interfaces
349  * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk
372  * clk_hw_register_fixed_rate - register fixed-rate clock with the clock
377  * @flags: framework-specific flags
378  * @fixed_rate: non-adjustable clock rate
385  * devm_clk_hw_register_fixed_rate - register fixed-rate clock with the clock
390  * @flags: framework-specific flags
391  * @fixed_rate: non-adjustable clock rate
397  * devm_clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
401  * @parent_data: parent clk data
402  * @flags: framework-specific flags
403  * @fixed_rate: non-adjustable clock rate
411  * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with
416  * @flags: framework-specific flags
417  * @fixed_rate: non-adjustable clock rate
424  * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
428  * @parent_data: parent clk data
429  * @flags: framework-specific flags
430  * @fixed_rate: non-adjustable clock rate
438  * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
443  * @flags: framework-specific flags
444  * @fixed_rate: non-adjustable clock rate
445  * @fixed_accuracy: non-adjustable clock accuracy
454  * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate
459  * @flags: framework-specific flags
460  * @fixed_rate: non-adjustable clock rate
461  * @fixed_accuracy: non-adjustable clock accuracy
469  * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate
474  * @flags: framework-specific flags
475  * @fixed_rate: non-adjustable clock rate
476  * @fixed_accuracy: non-adjustable clock accuracy
484  * clk_hw_register_fixed_rate_parent_accuracy - register fixed-rate clock with
489  * @flags: framework-specific flags
490  * @fixed_rate: non-adjustable clock rate
504  * struct clk_gate - gating clock
506  * @hw:		handle between common and hardware-specific interfaces
509  * @flags:	hardware-specific flags
515  * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
518  * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
519  *	of this register, and mask of gate bits are in higher 16-bit of this
520  *	register.  While setting the gate bits, higher 16-bit should also be
522  * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
560  * clk_hw_register_gate - register a gate clock with the clock framework
564  * @flags: framework-specific flags for this clock
567  * @clk_gate_flags: gate-specific flags for this clock
576  * clk_hw_register_gate_parent_hw - register a gate clock with the clock
581  * @flags: framework-specific flags for this clock
584  * @clk_gate_flags: gate-specific flags for this clock
593  * clk_hw_register_gate_parent_data - register a gate clock with the clock
597  * @parent_data: parent clk data
598  * @flags: framework-specific flags for this clock
601  * @clk_gate_flags: gate-specific flags for this clock
610  * devm_clk_hw_register_gate - register a gate clock with the clock framework
614  * @flags: framework-specific flags for this clock
617  * @clk_gate_flags: gate-specific flags for this clock
626  * devm_clk_hw_register_gate_parent_data - register a gate clock with the
630  * @parent_data: parent clk data
631  * @flags: framework-specific flags for this clock
634  * @clk_gate_flags: gate-specific flags for this clock
654  * struct clk_divider - adjustable divider clock
656  * @hw:		handle between common and hardware-specific interfaces
658  * @shift:	shift to the divider bit field
667  * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
671  * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
673  * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors.  For dividers which have
678  * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
679  *	of this register, and mask of divider bits are in higher 16-bit of this
680  *	register.  While setting the divider bits, higher 16-bit should also be
682  * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
684  * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
686  * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
689  * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
696 	u8		shift;  member
703 #define clk_div_mask(width)	((1 << (width)) - 1)
743 		void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
749 		void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
753 		void __iomem *reg, u8 shift, u8 width,
757  * clk_register_divider - register a divider clock with the clock framework
761  * @flags: framework-specific flags
763  * @shift: number of bits to shift the bitfield
765  * @clk_divider_flags: divider-specific flags for this clock
768 #define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \  argument
771 				   (reg), (shift), (width),		       \
774  * clk_hw_register_divider - register a divider clock with the clock framework
778  * @flags: framework-specific flags
780  * @shift: number of bits to shift the bitfield
782  * @clk_divider_flags: divider-specific flags for this clock
785 #define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift,    \  argument
788 				  NULL, (flags), (reg), (shift), (width),     \
791  * clk_hw_register_divider_parent_hw - register a divider clock with the clock
796  * @flags: framework-specific flags
798  * @shift: number of bits to shift the bitfield
800  * @clk_divider_flags: divider-specific flags for this clock
804 					  shift, width, clk_divider_flags,    \  argument
807 				  NULL, (flags), (reg), (shift), (width),     \
810  * clk_hw_register_divider_parent_data - register a divider clock with the clock
814  * @parent_data: parent clk data
815  * @flags: framework-specific flags
817  * @shift: number of bits to shift the bitfield
819  * @clk_divider_flags: divider-specific flags for this clock
823 					    reg, shift, width,		      \  argument
826 				  (parent_data), (flags), (reg), (shift),     \
829  * clk_hw_register_divider_table - register a table based divider clock with
834  * @flags: framework-specific flags
836  * @shift: number of bits to shift the bitfield
838  * @clk_divider_flags: divider-specific flags for this clock
843 				      shift, width, clk_divider_flags, table, \  argument
846 				  NULL, (flags), (reg), (shift), (width),     \
849  * clk_hw_register_divider_table_parent_hw - register a table based divider
854  * @flags: framework-specific flags
856  * @shift: number of bits to shift the bitfield
858  * @clk_divider_flags: divider-specific flags for this clock
863 						reg, shift, width,	      \  argument
867 				  NULL, (flags), (reg), (shift), (width),     \
870  * clk_hw_register_divider_table_parent_data - register a table based divider
874  * @parent_data: parent clk data
875  * @flags: framework-specific flags
877  * @shift: number of bits to shift the bitfield
879  * @clk_divider_flags: divider-specific flags for this clock
884 						  flags, reg, shift, width,   \  argument
888 				  (parent_data), (flags), (reg), (shift),     \
892  * devm_clk_hw_register_divider - register a divider clock with the clock framework
896  * @flags: framework-specific flags
898  * @shift: number of bits to shift the bitfield
900  * @clk_divider_flags: divider-specific flags for this clock
903 #define devm_clk_hw_register_divider(dev, name, parent_name, flags, reg, shift,    \  argument
906 				  NULL, (flags), (reg), (shift), (width),     \
909  * devm_clk_hw_register_divider_parent_hw - register a divider clock with the clock framework
913  * @flags: framework-specific flags
915  * @shift: number of bits to shift the bitfield
917  * @clk_divider_flags: divider-specific flags for this clock
921 					       reg, shift, width,	      \  argument
925 				       (shift), (width), (clk_divider_flags), \
928  * devm_clk_hw_register_divider_table - register a table based divider clock
933  * @flags: framework-specific flags
935  * @shift: number of bits to shift the bitfield
937  * @clk_divider_flags: divider-specific flags for this clock
942 					   reg, shift, width,		      \  argument
945 				       NULL, NULL, (flags), (reg), (shift),   \
953  * struct clk_mux - multiplexer clock
955  * @hw:		handle between common and hardware-specific interfaces
958  * @shift:	shift to multiplexer bit field
960  * @flags:	hardware-specific flags
967  * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
968  * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
969  * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
970  *	register, and mask of mux bits are in higher 16-bit of this register.
971  *	While setting the mux bits, higher 16-bit should also be updated to
973  * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
975  * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
977  * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
986 	u8		shift;  member
1008 		unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
1015 		unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
1019 		unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
1023 			 shift, width, clk_mux_flags, lock)		      \  argument
1025 			       (flags), (reg), (shift), BIT((width)) - 1,     \
1028 				  flags, reg, shift, mask, clk_mux_flags,     \  argument
1032 			      (shift), (mask), (clk_mux_flags), (table),      \
1035 				  num_parents, flags, reg, shift, mask,	      \  argument
1039 			      (shift), (mask), (clk_mux_flags), (table),      \
1042 			    shift, width, clk_mux_flags, lock)		      \  argument
1045 			      (shift), BIT((width)) - 1, (clk_mux_flags),     \
1048 				reg, shift, width, clk_mux_flags, lock)	      \  argument
1050 			      (parent_hws), NULL, (flags), (reg), (shift),    \
1051 			      BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
1053 					flags, reg, shift, width,	      \  argument
1056 			      (parent_data), (flags), (reg), (shift),	      \
1057 			      BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
1059 					      num_parents, flags, reg, shift, \  argument
1063 			      (parent_data), (flags), (reg), (shift),	      \
1064 			      BIT((width)) - 1, (clk_mux_flags), table, (lock))
1066 			    shift, width, clk_mux_flags, lock)		      \  argument
1069 			      (shift), BIT((width)) - 1, (clk_mux_flags),     \
1072 					    num_parents, flags, reg, shift,   \  argument
1076 				   (shift), BIT((width)) - 1,		      \
1079 					      num_parents, flags, reg, shift, \  argument
1083 			      NULL, (parent_data), (flags), (reg), (shift),   \
1084 			      BIT((width)) - 1, (clk_mux_flags), table, (lock))
1096  * struct clk_fixed_factor - fixed multiplier and divider clock
1098  * @hw:		handle between common and hardware-specific interfaces
1109  * * CLK_FIXED_FACTOR_FIXED_ACCURACY - Use the value in @acc instead of the
1163  * struct clk_fractional_divider - adjustable fractional divider clock
1165  * @hw:		handle between common and hardware-specific interfaces
1167  * @mshift:	shift to the numerator bit field
1169  * @nshift:	shift to the denominator bit field
1177  * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
1181  * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
1184  * CLK_FRAC_DIVIDER_POWER_OF_TWO_PS - By default the resulting fraction might
1187  *	to shift left by a few bits in case, when the asked one is quite small
1189  *	caller's side the power-of-two capable prescaler exists.
1222  * struct clk_multiplier - adjustable multiplier clock
1224  * @hw:		handle between common and hardware-specific interfaces
1226  * @shift:	shift to the multiplier bit field
1234  * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
1239  * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
1241  * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
1248 	u8		shift;  member
1263  * struct clk_composite - aggregate clock of mux, divider and gate clocks
1265  * @hw:		handle between common and hardware-specific interfaces
1266  * @mux_hw:	handle between composite and hardware-specific mux clock
1267  * @rate_hw:	handle between composite and hardware-specific rate clock
1268  * @gate_hw:	handle between composite and hardware-specific gate clock
1385 	dst->clk = src->clk;  in __clk_hw_set_clk()
1386 	dst->core = src->core;  in __clk_hw_set_clk()
1574 						   void *data),
1575 			void *data);
1578 						 void *data),
1579 			   void *data);
1582 						 void *data),
1583 			   void *data);
1587 				  void *data);
1589 				    void *data);
1590 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
1592 				     void *data);
1602 						   void *data),  in of_clk_add_provider()  argument
1603 			void *data)  in of_clk_add_provider()
1609 					      void *data),  in of_clk_add_hw_provider()  argument
1610 			void *data)  in of_clk_add_hw_provider()
1616 						 void *data),  in devm_of_clk_add_hw_provider()  argument
1617 			   void *data)  in devm_of_clk_add_hw_provider()
1624 	struct of_phandle_args *clkspec, void *data)  in of_clk_src_simple_get()  argument
1626 	return ERR_PTR(-ENOENT);  in of_clk_src_simple_get()
1629 of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data)  in of_clk_hw_simple_get()  argument
1631 	return ERR_PTR(-ENOENT);  in of_clk_hw_simple_get()
1634 	struct of_phandle_args *clkspec, void *data)  in of_clk_src_onecell_get()  argument
1636 	return ERR_PTR(-ENOENT);  in of_clk_src_onecell_get()
1639 of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)  in of_clk_hw_onecell_get()  argument
1641 	return ERR_PTR(-ENOENT);  in of_clk_hw_onecell_get()