clk/meson/s4-pll.c

1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
5  * Copyright (c) 2022-2023 Amlogic, inc. All rights reserved
9 #include <linux/clk-provider.h>
13 #include "clk-mpll.h"
14 #include "clk-pll.h"
15 #include "clk-regmap.h"
16 #include "s4-pll.h"
17 #include "meson-clkc-utils.h"
18 #include <dt-bindings/clock/amlogic,s4-pll-clkc.h>
25  * in the kernel phase. Write of fixed PLL-related register will cause the system to crash.
30 	.data = &(struct meson_clk_pll_data){
33 			.shift   = 28,
38 			.shift   = 0,
43 			.shift   = 0,
48 			.shift   = 10,
53 			.shift   = 31,
58 			.shift   = 29,
73 	.data = &(struct clk_regmap_div_data){
75 		.shift = 16,
105 	.data = &(struct clk_regmap_gate_data){
131 	.data = &(struct clk_regmap_gate_data){
157 	.data = &(struct clk_regmap_gate_data){
183 	.data = &(struct clk_regmap_gate_data){
209 	.data = &(struct clk_regmap_gate_data){
237 	.data = &(struct clk_regmap_gate_data){
269 	.data = &(struct meson_clk_pll_data){
272 			.shift   = 28,
277 			.shift   = 0,
282 			.shift   = 10,
287 			.shift   = 31,
292 			.shift   = 29,
310 	.data = &(struct clk_regmap_div_data){
312 		.shift = 16,
341 	.data = &(struct meson_clk_pll_data){
344 			.shift   = 28,
349 			.shift   = 0,
354 			.shift   = 10,
359 			.shift   = 31,
364 			.shift   = 29,
383 	.data = &(struct clk_regmap_div_data){
385 		.shift = 16,
402 	.data = &(struct meson_clk_pll_data){
405 			.shift   = 28,
410 			.shift   = 0,
415 			.shift   = 10,
420 			.shift   = 31,
425 			.shift   = 29,
441 	.data = &(struct clk_regmap_div_data){
443 		.shift = 16,
459 	.data = &(struct clk_regmap_div_data){
461 		.shift = 20,
490 	.data = &(struct clk_regmap_mux_data){
493 		.shift = 5,
524 	.data = &(struct meson_clk_mpll_data){
527 			.shift   = 0,
532 			.shift   = 30,
537 			.shift   = 20,
542 			.shift   = 29,
560 	.data = &(struct clk_regmap_gate_data){
578 	.data = &(struct meson_clk_mpll_data){
581 			.shift   = 0,
586 			.shift   = 30,
591 			.shift   = 20,
596 			.shift   = 29,
614 	.data = &(struct clk_regmap_gate_data){
632 	.data = &(struct meson_clk_mpll_data){
635 			.shift   = 0,
640 			.shift   = 30,
645 			.shift   = 20,
650 			.shift   = 29,
668 	.data = &(struct clk_regmap_gate_data){
686 	.data = &(struct meson_clk_mpll_data){
689 			.shift   = 0,
694 			.shift   = 30,
699 			.shift   = 20,
704 			.shift   = 29,
722 	.data = &(struct clk_regmap_gate_data){
816 	struct device *dev = &pdev->dev;  in meson_s4_pll_probe()
838 		s4_pll_clk_regmaps[i]->map = regmap;  in meson_s4_pll_probe()
858 		.compatible = "amlogic,s4-pll-clkc",
867 		.name	= "s4-pll-clkc",