Lines Matching +full:data +full:- +full:shift
1 // SPDX-License-Identifier: GPL-2.0
14 #include "sprd-mcdt.h"
121 u32 orig = readl_relaxed(mcdt->base + reg); in sprd_mcdt_update()
125 writel_relaxed(tmp, mcdt->base + reg); in sprd_mcdt_update()
155 u32 shift = MCDT_DAC_DMA_SHIFT + channel; in sprd_mcdt_dac_dma_enable() local
158 sprd_mcdt_update(mcdt, MCDT_DMA_EN, BIT(shift), BIT(shift)); in sprd_mcdt_dac_dma_enable()
160 sprd_mcdt_update(mcdt, MCDT_DMA_EN, 0, BIT(shift)); in sprd_mcdt_dac_dma_enable()
187 writel_relaxed(val, mcdt->base + reg); in sprd_mcdt_dac_write_fifo()
195 *val = readl_relaxed(mcdt->base + reg); in sprd_mcdt_adc_read_fifo()
298 u32 reg, shift = sprd_mcdt_dma_ack_shift(channel), ack = dma_chan; in sprd_mcdt_dac_dma_ack_select() local
313 sprd_mcdt_update(mcdt, reg, ack << shift, in sprd_mcdt_dac_dma_ack_select()
314 MCDT_DMA_ACK_SEL_MASK << shift); in sprd_mcdt_dac_dma_ack_select()
320 u32 reg, shift = sprd_mcdt_dma_ack_shift(channel), ack = dma_chan; in sprd_mcdt_adc_dma_ack_select() local
335 sprd_mcdt_update(mcdt, reg, ack << shift, in sprd_mcdt_adc_dma_ack_select()
336 MCDT_DMA_ACK_SEL_MASK << shift); in sprd_mcdt_adc_dma_ack_select()
342 u32 reg, shift; in sprd_mcdt_chan_fifo_sts() local
362 shift = fifo_sts; in sprd_mcdt_chan_fifo_sts()
368 shift = 8 + fifo_sts; in sprd_mcdt_chan_fifo_sts()
373 shift = 16 + fifo_sts; in sprd_mcdt_chan_fifo_sts()
378 shift = 24 + fifo_sts; in sprd_mcdt_chan_fifo_sts()
385 return !!(readl_relaxed(mcdt->base + reg) & BIT(shift)); in sprd_mcdt_chan_fifo_sts()
395 u32 shift = MCDT_ADC_FIFO_SHIFT + channel; in sprd_mcdt_adc_fifo_clear() local
397 sprd_mcdt_update(mcdt, MCDT_FIFO_CLR, BIT(shift), BIT(shift)); in sprd_mcdt_adc_fifo_clear()
403 u32 r_addr = (readl_relaxed(mcdt->base + reg) >> in sprd_mcdt_dac_fifo_avail()
405 u32 w_addr = readl_relaxed(mcdt->base + reg) & MCDT_CH_FIFO_ADDR_MASK; in sprd_mcdt_dac_fifo_avail()
408 return 4 * (MCDT_FIFO_LENGTH - w_addr + r_addr); in sprd_mcdt_dac_fifo_avail()
410 return 4 * (r_addr - w_addr); in sprd_mcdt_dac_fifo_avail()
416 u32 r_addr = (readl_relaxed(mcdt->base + reg) >> in sprd_mcdt_adc_fifo_avail()
418 u32 w_addr = readl_relaxed(mcdt->base + reg) & MCDT_CH_FIFO_ADDR_MASK; in sprd_mcdt_adc_fifo_avail()
421 return 4 * (w_addr - r_addr); in sprd_mcdt_adc_fifo_avail()
423 return 4 * (MCDT_FIFO_LENGTH - r_addr + w_addr); in sprd_mcdt_adc_fifo_avail()
456 u32 reg, shift = sprd_mcdt_int_type_shift(channel, int_type); in sprd_mcdt_chan_int_en() local
473 sprd_mcdt_update(mcdt, reg, BIT(shift), BIT(shift)); in sprd_mcdt_chan_int_en()
475 sprd_mcdt_update(mcdt, reg, 0, BIT(shift)); in sprd_mcdt_chan_int_en()
481 u32 reg, shift = sprd_mcdt_int_type_shift(channel, int_type); in sprd_mcdt_chan_int_clear() local
497 sprd_mcdt_update(mcdt, reg, BIT(shift), BIT(shift)); in sprd_mcdt_chan_int_clear()
503 u32 reg, shift = sprd_mcdt_int_type_shift(channel, int_type); in sprd_mcdt_chan_int_sts() local
519 return !!(readl_relaxed(mcdt->base + reg) & BIT(shift)); in sprd_mcdt_chan_int_sts()
527 spin_lock(&mcdt->lock); in sprd_mcdt_irq_handler()
531 struct sprd_mcdt_chan *chan = &mcdt->chan[i]; in sprd_mcdt_irq_handler()
534 if (chan->cb) in sprd_mcdt_irq_handler()
535 chan->cb->notify(chan->cb->data); in sprd_mcdt_irq_handler()
542 &mcdt->chan[i + MCDT_ADC_CHANNEL_NUM]; in sprd_mcdt_irq_handler()
545 if (chan->cb) in sprd_mcdt_irq_handler()
546 chan->cb->notify(chan->cb->data); in sprd_mcdt_irq_handler()
550 spin_unlock(&mcdt->lock); in sprd_mcdt_irq_handler()
556 * sprd_mcdt_chan_write - write data to the MCDT channel's fifo
559 * @size: data size
561 * Note: We can not write data to the channel fifo when enabling the DMA mode,
562 * otherwise the channel fifo data will be invalid.
571 struct sprd_mcdt_dev *mcdt = chan->mcdt; in sprd_mcdt_chan_write()
576 spin_lock_irqsave(&mcdt->lock, flags); in sprd_mcdt_chan_write()
578 if (chan->dma_enable) { in sprd_mcdt_chan_write()
579 dev_err(mcdt->dev, in sprd_mcdt_chan_write()
580 "Can not write data when DMA mode enabled\n"); in sprd_mcdt_chan_write()
581 spin_unlock_irqrestore(&mcdt->lock, flags); in sprd_mcdt_chan_write()
582 return -EINVAL; in sprd_mcdt_chan_write()
585 if (sprd_mcdt_chan_fifo_sts(mcdt, chan->id, MCDT_DAC_FIFO_REAL_FULL)) { in sprd_mcdt_chan_write()
586 dev_err(mcdt->dev, "Channel fifo is full now\n"); in sprd_mcdt_chan_write()
587 spin_unlock_irqrestore(&mcdt->lock, flags); in sprd_mcdt_chan_write()
588 return -EBUSY; in sprd_mcdt_chan_write()
591 avail = sprd_mcdt_dac_fifo_avail(mcdt, chan->id); in sprd_mcdt_chan_write()
593 dev_err(mcdt->dev, in sprd_mcdt_chan_write()
594 "Data size is larger than the available fifo size\n"); in sprd_mcdt_chan_write()
595 spin_unlock_irqrestore(&mcdt->lock, flags); in sprd_mcdt_chan_write()
596 return -EBUSY; in sprd_mcdt_chan_write()
600 sprd_mcdt_dac_write_fifo(mcdt, chan->id, *buf++); in sprd_mcdt_chan_write()
602 spin_unlock_irqrestore(&mcdt->lock, flags); in sprd_mcdt_chan_write()
608 * sprd_mcdt_chan_read - read data from the MCDT channel's fifo
611 * @size: data size
613 * Note: We can not read data from the channel fifo when enabling the DMA mode,
614 * otherwise the reading data will be invalid.
616 * Usually user need start to read data once receiving the fifo full interrupt.
618 * Returns data size of reading successfully, or an error code on failure.
622 struct sprd_mcdt_dev *mcdt = chan->mcdt; in sprd_mcdt_chan_read()
627 spin_lock_irqsave(&mcdt->lock, flags); in sprd_mcdt_chan_read()
629 if (chan->dma_enable) { in sprd_mcdt_chan_read()
630 dev_err(mcdt->dev, "Can not read data when DMA mode enabled\n"); in sprd_mcdt_chan_read()
631 spin_unlock_irqrestore(&mcdt->lock, flags); in sprd_mcdt_chan_read()
632 return -EINVAL; in sprd_mcdt_chan_read()
635 if (sprd_mcdt_chan_fifo_sts(mcdt, chan->id, MCDT_ADC_FIFO_REAL_EMPTY)) { in sprd_mcdt_chan_read()
636 dev_err(mcdt->dev, "Channel fifo is empty\n"); in sprd_mcdt_chan_read()
637 spin_unlock_irqrestore(&mcdt->lock, flags); in sprd_mcdt_chan_read()
638 return -EBUSY; in sprd_mcdt_chan_read()
641 avail = sprd_mcdt_adc_fifo_avail(mcdt, chan->id); in sprd_mcdt_chan_read()
646 sprd_mcdt_adc_read_fifo(mcdt, chan->id, buf++); in sprd_mcdt_chan_read()
648 spin_unlock_irqrestore(&mcdt->lock, flags); in sprd_mcdt_chan_read()
654 * sprd_mcdt_chan_int_enable - enable the interrupt mode for the MCDT channel
662 * data manually.
664 * For ADC channel, user can start to read data once receiving one fifo full
665 * interrupt. For DAC channel, user can start to write data once receiving one
666 * fifo empty interrupt or just call sprd_mcdt_chan_write() to write data
674 struct sprd_mcdt_dev *mcdt = chan->mcdt; in sprd_mcdt_chan_int_enable()
678 spin_lock_irqsave(&mcdt->lock, flags); in sprd_mcdt_chan_int_enable()
680 if (chan->dma_enable || chan->int_enable) { in sprd_mcdt_chan_int_enable()
681 dev_err(mcdt->dev, "Failed to set interrupt mode.\n"); in sprd_mcdt_chan_int_enable()
682 spin_unlock_irqrestore(&mcdt->lock, flags); in sprd_mcdt_chan_int_enable()
683 return -EINVAL; in sprd_mcdt_chan_int_enable()
686 switch (chan->type) { in sprd_mcdt_chan_int_enable()
688 sprd_mcdt_adc_fifo_clear(mcdt, chan->id); in sprd_mcdt_chan_int_enable()
689 sprd_mcdt_adc_set_watermark(mcdt, chan->id, water_mark, in sprd_mcdt_chan_int_enable()
690 MCDT_FIFO_LENGTH - 1); in sprd_mcdt_chan_int_enable()
691 sprd_mcdt_chan_int_en(mcdt, chan->id, in sprd_mcdt_chan_int_enable()
693 sprd_mcdt_ap_int_enable(mcdt, chan->id, true); in sprd_mcdt_chan_int_enable()
697 sprd_mcdt_dac_fifo_clear(mcdt, chan->id); in sprd_mcdt_chan_int_enable()
698 sprd_mcdt_dac_set_watermark(mcdt, chan->id, in sprd_mcdt_chan_int_enable()
699 MCDT_FIFO_LENGTH - 1, water_mark); in sprd_mcdt_chan_int_enable()
700 sprd_mcdt_chan_int_en(mcdt, chan->id, in sprd_mcdt_chan_int_enable()
702 sprd_mcdt_ap_int_enable(mcdt, chan->id, true); in sprd_mcdt_chan_int_enable()
706 dev_err(mcdt->dev, "Unsupported channel type\n"); in sprd_mcdt_chan_int_enable()
707 ret = -EINVAL; in sprd_mcdt_chan_int_enable()
711 chan->cb = cb; in sprd_mcdt_chan_int_enable()
712 chan->int_enable = true; in sprd_mcdt_chan_int_enable()
715 spin_unlock_irqrestore(&mcdt->lock, flags); in sprd_mcdt_chan_int_enable()
722 * sprd_mcdt_chan_int_disable - disable the interrupt mode for the MCDT channel
727 struct sprd_mcdt_dev *mcdt = chan->mcdt; in sprd_mcdt_chan_int_disable()
730 spin_lock_irqsave(&mcdt->lock, flags); in sprd_mcdt_chan_int_disable()
732 if (!chan->int_enable) { in sprd_mcdt_chan_int_disable()
733 spin_unlock_irqrestore(&mcdt->lock, flags); in sprd_mcdt_chan_int_disable()
737 switch (chan->type) { in sprd_mcdt_chan_int_disable()
739 sprd_mcdt_chan_int_en(mcdt, chan->id, in sprd_mcdt_chan_int_disable()
741 sprd_mcdt_chan_int_clear(mcdt, chan->id, MCDT_ADC_FIFO_AF_INT); in sprd_mcdt_chan_int_disable()
742 sprd_mcdt_ap_int_enable(mcdt, chan->id, false); in sprd_mcdt_chan_int_disable()
746 sprd_mcdt_chan_int_en(mcdt, chan->id, in sprd_mcdt_chan_int_disable()
748 sprd_mcdt_chan_int_clear(mcdt, chan->id, MCDT_DAC_FIFO_AE_INT); in sprd_mcdt_chan_int_disable()
749 sprd_mcdt_ap_int_enable(mcdt, chan->id, false); in sprd_mcdt_chan_int_disable()
756 chan->int_enable = false; in sprd_mcdt_chan_int_disable()
757 spin_unlock_irqrestore(&mcdt->lock, flags); in sprd_mcdt_chan_int_disable()
762 * sprd_mcdt_chan_dma_enable - enable the DMA mode for the MCDT channel
768 * transfer data to the channel fifo and do not need reading/writing data
777 struct sprd_mcdt_dev *mcdt = chan->mcdt; in sprd_mcdt_chan_dma_enable()
781 spin_lock_irqsave(&mcdt->lock, flags); in sprd_mcdt_chan_dma_enable()
783 if (chan->dma_enable || chan->int_enable || in sprd_mcdt_chan_dma_enable()
785 dev_err(mcdt->dev, "Failed to set DMA mode\n"); in sprd_mcdt_chan_dma_enable()
786 spin_unlock_irqrestore(&mcdt->lock, flags); in sprd_mcdt_chan_dma_enable()
787 return -EINVAL; in sprd_mcdt_chan_dma_enable()
790 switch (chan->type) { in sprd_mcdt_chan_dma_enable()
792 sprd_mcdt_adc_fifo_clear(mcdt, chan->id); in sprd_mcdt_chan_dma_enable()
793 sprd_mcdt_adc_set_watermark(mcdt, chan->id, in sprd_mcdt_chan_dma_enable()
794 water_mark, MCDT_FIFO_LENGTH - 1); in sprd_mcdt_chan_dma_enable()
795 sprd_mcdt_adc_dma_enable(mcdt, chan->id, true); in sprd_mcdt_chan_dma_enable()
796 sprd_mcdt_adc_dma_chn_select(mcdt, chan->id, dma_chan); in sprd_mcdt_chan_dma_enable()
797 sprd_mcdt_adc_dma_ack_select(mcdt, chan->id, dma_chan); in sprd_mcdt_chan_dma_enable()
801 sprd_mcdt_dac_fifo_clear(mcdt, chan->id); in sprd_mcdt_chan_dma_enable()
802 sprd_mcdt_dac_set_watermark(mcdt, chan->id, in sprd_mcdt_chan_dma_enable()
803 MCDT_FIFO_LENGTH - 1, water_mark); in sprd_mcdt_chan_dma_enable()
804 sprd_mcdt_dac_dma_enable(mcdt, chan->id, true); in sprd_mcdt_chan_dma_enable()
805 sprd_mcdt_dac_dma_chn_select(mcdt, chan->id, dma_chan); in sprd_mcdt_chan_dma_enable()
806 sprd_mcdt_dac_dma_ack_select(mcdt, chan->id, dma_chan); in sprd_mcdt_chan_dma_enable()
810 dev_err(mcdt->dev, "Unsupported channel type\n"); in sprd_mcdt_chan_dma_enable()
811 ret = -EINVAL; in sprd_mcdt_chan_dma_enable()
815 chan->dma_enable = true; in sprd_mcdt_chan_dma_enable()
817 spin_unlock_irqrestore(&mcdt->lock, flags); in sprd_mcdt_chan_dma_enable()
824 * sprd_mcdt_chan_dma_disable - disable the DMA mode for the MCDT channel
829 struct sprd_mcdt_dev *mcdt = chan->mcdt; in sprd_mcdt_chan_dma_disable()
832 spin_lock_irqsave(&mcdt->lock, flags); in sprd_mcdt_chan_dma_disable()
834 if (!chan->dma_enable) { in sprd_mcdt_chan_dma_disable()
835 spin_unlock_irqrestore(&mcdt->lock, flags); in sprd_mcdt_chan_dma_disable()
839 switch (chan->type) { in sprd_mcdt_chan_dma_disable()
841 sprd_mcdt_adc_dma_enable(mcdt, chan->id, false); in sprd_mcdt_chan_dma_disable()
842 sprd_mcdt_adc_fifo_clear(mcdt, chan->id); in sprd_mcdt_chan_dma_disable()
846 sprd_mcdt_dac_dma_enable(mcdt, chan->id, false); in sprd_mcdt_chan_dma_disable()
847 sprd_mcdt_dac_fifo_clear(mcdt, chan->id); in sprd_mcdt_chan_dma_disable()
854 chan->dma_enable = false; in sprd_mcdt_chan_dma_disable()
855 spin_unlock_irqrestore(&mcdt->lock, flags); in sprd_mcdt_chan_dma_disable()
860 * sprd_mcdt_request_chan - request one MCDT channel
874 if (temp->type == type && temp->id == channel) { in sprd_mcdt_request_chan()
875 list_del_init(&temp->list); in sprd_mcdt_request_chan()
890 * sprd_mcdt_free_chan - free one MCDT channel
909 list_add_tail(&chan->list, &sprd_mcdt_chan_list); in sprd_mcdt_free_chan()
920 struct sprd_mcdt_chan *chan = &mcdt->chan[i]; in sprd_mcdt_init_chans()
923 chan->id = i; in sprd_mcdt_init_chans()
924 chan->type = SPRD_MCDT_ADC_CHAN; in sprd_mcdt_init_chans()
925 chan->fifo_phys = res->start + MCDT_CH0_RXD + i * 4; in sprd_mcdt_init_chans()
927 chan->id = i - MCDT_ADC_CHANNEL_NUM; in sprd_mcdt_init_chans()
928 chan->type = SPRD_MCDT_DAC_CHAN; in sprd_mcdt_init_chans()
929 chan->fifo_phys = res->start + MCDT_CH0_TXD + in sprd_mcdt_init_chans()
930 (i - MCDT_ADC_CHANNEL_NUM) * 4; in sprd_mcdt_init_chans()
933 chan->mcdt = mcdt; in sprd_mcdt_init_chans()
934 INIT_LIST_HEAD(&chan->list); in sprd_mcdt_init_chans()
937 list_add_tail(&chan->list, &sprd_mcdt_chan_list); in sprd_mcdt_init_chans()
948 mcdt = devm_kzalloc(&pdev->dev, sizeof(*mcdt), GFP_KERNEL); in sprd_mcdt_probe()
950 return -ENOMEM; in sprd_mcdt_probe()
952 mcdt->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in sprd_mcdt_probe()
953 if (IS_ERR(mcdt->base)) in sprd_mcdt_probe()
954 return PTR_ERR(mcdt->base); in sprd_mcdt_probe()
956 mcdt->dev = &pdev->dev; in sprd_mcdt_probe()
957 spin_lock_init(&mcdt->lock); in sprd_mcdt_probe()
964 ret = devm_request_irq(&pdev->dev, irq, sprd_mcdt_irq_handler, in sprd_mcdt_probe()
965 0, "sprd-mcdt", mcdt); in sprd_mcdt_probe()
967 dev_err(&pdev->dev, "Failed to request MCDT IRQ\n"); in sprd_mcdt_probe()
983 list_del(&chan->list); in sprd_mcdt_remove()
989 { .compatible = "sprd,sc9860-mcdt", },
998 .name = "sprd-mcdt",
1005 MODULE_DESCRIPTION("Spreadtrum Multi-Channel Data Transfer Driver");