Lines Matching +full:data +full:- +full:shift
1 // SPDX-License-Identifier: GPL-2.0+
3 * AmLogic Meson-AXG Clock Controller Driver
12 #include <linux/clk-provider.h>
18 #include "clk-regmap.h"
19 #include "clk-pll.h"
20 #include "clk-mpll.h"
22 #include "meson-eeclk.h"
24 #include <dt-bindings/clock/axg-clkc.h>
29 .data = &(struct meson_clk_pll_data){
32 .shift = 30,
37 .shift = 0,
42 .shift = 9,
47 .shift = 0,
52 .shift = 31,
57 .shift = 29,
72 .data = &(struct clk_regmap_div_data){
74 .shift = 16,
93 .data = &(struct meson_clk_pll_data){
96 .shift = 30,
101 .shift = 0,
106 .shift = 9,
111 .shift = 31,
116 .shift = 29,
131 .data = &(struct clk_regmap_div_data){
133 .shift = 16,
190 .data = &(struct meson_clk_pll_data){
193 .shift = 30,
198 .shift = 0,
203 .shift = 9,
208 .shift = 0,
213 .shift = 31,
218 .shift = 29,
236 .data = &(struct clk_regmap_div_data){
238 .shift = 16,
262 .data = &(struct meson_clk_pll_data){
265 .shift = 30,
270 .shift = 0,
275 .shift = 9,
280 .shift = 0,
285 .shift = 31,
290 .shift = 29,
309 .data = &(struct clk_regmap_div_data){
311 .shift = 16,
338 .data = &(struct clk_regmap_gate_data){
365 .data = &(struct clk_regmap_gate_data){
384 * b) CCF has a clock hand-off mechanism to make the sure the
403 .data = &(struct clk_regmap_gate_data){
429 .data = &(struct clk_regmap_gate_data){
457 .data = &(struct clk_regmap_gate_data){
472 .data = &(struct clk_regmap_div_data){
474 .shift = 12,
488 .data = &(struct meson_clk_mpll_data){
491 .shift = 0,
496 .shift = 15,
501 .shift = 16,
506 .shift = 0,
523 .data = &(struct clk_regmap_gate_data){
539 .data = &(struct meson_clk_mpll_data){
542 .shift = 0,
547 .shift = 15,
552 .shift = 16,
557 .shift = 1,
574 .data = &(struct clk_regmap_gate_data){
590 .data = &(struct meson_clk_mpll_data){
593 .shift = 0,
598 .shift = 15,
603 .shift = 16,
608 .shift = 25,
613 .shift = 2,
630 .data = &(struct clk_regmap_gate_data){
646 .data = &(struct meson_clk_mpll_data){
649 .shift = 12,
654 .shift = 11,
659 .shift = 2,
664 .shift = 3,
681 .data = &(struct clk_regmap_gate_data){
715 .data = &(struct meson_clk_pll_data){
718 .shift = 30,
723 .shift = 0,
728 .shift = 9,
733 .shift = 0,
738 .shift = 31,
743 .shift = 29,
761 .data = &(struct clk_regmap_div_data){
763 .shift = 16,
779 .data = &(struct clk_regmap_div_data){
781 .shift = 6,
797 .data = &(struct clk_regmap_mux_data){
800 .shift = 2,
814 .data = &(struct clk_regmap_mux_data){
817 .shift = 1,
831 .data = &(struct clk_regmap_gate_data){
846 .data = &(struct clk_regmap_gate_data){
871 .data = &(struct clk_regmap_mux_data){
874 .shift = 12,
886 .data = &(struct clk_regmap_div_data){
888 .shift = 0,
903 .data = &(struct clk_regmap_gate_data){
934 .data = &(struct clk_regmap_mux_data){
937 .shift = 25,
949 .data = &(struct clk_regmap_div_data){
951 .shift = 16,
967 .data = &(struct clk_regmap_gate_data){
984 .data = &(struct clk_regmap_mux_data){
987 .shift = 9,
999 .data = &(struct clk_regmap_div_data){
1001 .shift = 0,
1017 .data = &(struct clk_regmap_gate_data){
1042 .data = &(struct clk_regmap_mux_data){
1045 .shift = 9,
1058 .data = &(struct clk_regmap_div_data){
1060 .shift = 0,
1073 .data = &(struct clk_regmap_gate_data){
1091 .data = &(struct clk_regmap_mux_data){
1094 .shift = 25,
1107 .data = &(struct clk_regmap_div_data){
1109 .shift = 16,
1122 .data = &(struct clk_regmap_gate_data){
1140 .data = &(struct clk_regmap_mux_data){
1143 .shift = 31,
1160 .data = &(struct clk_regmap_mux_data){
1163 .shift = 9,
1175 .data = &(struct clk_regmap_div_data){
1177 .shift = 0,
1192 .data = &(struct clk_regmap_gate_data){
1208 .data = &(struct clk_regmap_mux_data){
1211 .shift = 25,
1223 .data = &(struct clk_regmap_div_data){
1225 .shift = 16,
1240 .data = &(struct clk_regmap_gate_data){
1256 .data = &(struct clk_regmap_mux_data){
1259 .shift = 31,
1274 .data = &(struct clk_regmap_gate_data){
1300 .data = &(struct clk_regmap_mux_data){
1303 .shift = 16,
1315 .data = &(struct clk_regmap_mux_data){
1318 .shift = 16,
1330 .data = &(struct clk_regmap_gate_data){
1344 .data = &(struct clk_regmap_gate_data){
1358 .data = &(struct clk_regmap_div_data){
1360 .shift = 0,
1375 .data = &(struct clk_regmap_div_data){
1377 .shift = 0,
1392 .data = &(struct clk_regmap_gate_data){
1406 .data = &(struct clk_regmap_gate_data){
1420 .data = &(struct clk_regmap_gate_data){
1434 .data = &(struct clk_regmap_gate_data){
1448 .data = &(struct clk_regmap_gate_data){
1462 .data = &(struct clk_regmap_gate_data){
1476 .data = &(struct clk_regmap_gate_data){
1490 .data = &(struct clk_regmap_gate_data){
1504 .data = &(struct clk_regmap_gate_data){
1518 .data = &(struct clk_regmap_gate_data){
1532 .data = &(struct clk_regmap_gate_data){
1546 .data = &(struct clk_regmap_gate_data){
1678 .data = &(struct clk_regmap_mux_data){
1681 .shift = 12,
1694 .data = &(struct clk_regmap_gate_data){
1722 .data = &(struct clk_regmap_mux_data){
1725 .shift = 21,
1739 .data = &(struct clk_regmap_div_data){
1741 .shift = 12,
1755 .data = &(struct clk_regmap_gate_data){
1786 .data = &(struct clk_regmap_mux_data){
1789 .shift = 12,
1807 .data = &(struct clk_regmap_div_data){
1809 .shift = 0,
1824 .data = &(struct clk_regmap_gate_data){
2174 { .compatible = "amlogic,axg-clkc", .data = &axg_clkc_data },
2182 .name = "axg-clkc",