Lines Matching +full:data +full:- +full:shift
1 // SPDX-License-Identifier: GPL-2.0+
3 * Amlogic Meson-G12A Clock Controller Driver
13 #include <linux/clk-provider.h>
20 #include "clk-mpll.h"
21 #include "clk-pll.h"
22 #include "clk-regmap.h"
23 #include "clk-cpu-dyndiv.h"
24 #include "vid-pll-div.h"
26 #include "meson-eeclk.h"
29 #include <dt-bindings/clock/g12a-clkc.h>
34 .data = &(struct meson_clk_pll_data){
37 .shift = 28,
42 .shift = 0,
47 .shift = 10,
52 .shift = 0,
57 .shift = 31,
62 .shift = 29,
77 .data = &(struct clk_regmap_div_data){
79 .shift = 16,
103 .data = &(struct meson_clk_pll_data){
106 .shift = 28,
111 .shift = 0,
116 .shift = 10,
121 .shift = 31,
126 .shift = 29,
144 .data = &(struct clk_regmap_div_data){
146 .shift = 16,
162 .data = &(struct meson_clk_pll_data){
165 .shift = 28,
170 .shift = 0,
175 .shift = 10,
180 .shift = 31,
185 .shift = 29,
203 .data = &(struct clk_regmap_div_data){
205 .shift = 16,
221 .data = &(struct clk_regmap_gate_data){
238 .data = &(struct clk_regmap_gate_data){
294 .data = &(struct clk_regmap_gate_data){
312 * b) CCF has a clock hand-off mechanism to make the sure the
331 .data = &(struct clk_regmap_gate_data){
348 * b) CCF has a clock hand-off mechanism to make the sure the
357 .data = &(struct clk_regmap_mux_data){
360 .shift = 0,
378 .data = &(struct clk_regmap_mux_data){
381 .shift = 16,
392 /* This sub-tree is used a parking clock */
399 .data = &(struct meson_clk_cpu_dyndiv_data){
402 .shift = 4,
407 .shift = 26,
424 .data = &(struct clk_regmap_mux_data){
427 .shift = 2,
444 .data = &(struct clk_regmap_div_data){
446 .shift = 20,
461 .data = &(struct clk_regmap_mux_data){
464 .shift = 18,
474 /* This sub-tree is used a parking clock */
481 .data = &(struct clk_regmap_mux_data){
484 .shift = 10,
501 .data = &(struct clk_regmap_mux_data){
504 .shift = 11,
521 .data = &(struct clk_regmap_mux_data){
524 .shift = 11,
541 .data = &(struct clk_regmap_mux_data){
544 .shift = 0,
562 .data = &(struct meson_clk_cpu_dyndiv_data){
565 .shift = 4,
570 .shift = 26,
587 .data = &(struct clk_regmap_mux_data){
590 .shift = 2,
607 .data = &(struct clk_regmap_mux_data){
610 .shift = 16,
621 /* This sub-tree is used a parking clock */
628 .data = &(struct clk_regmap_div_data){
630 .shift = 20,
645 .data = &(struct clk_regmap_mux_data){
648 .shift = 18,
658 /* This sub-tree is used a parking clock */
665 .data = &(struct clk_regmap_mux_data){
668 .shift = 10,
685 .data = &(struct clk_regmap_mux_data){
688 .shift = 11,
707 .data = &(struct clk_regmap_mux_data){
710 .shift = 0,
727 .data = &(struct clk_regmap_mux_data){
730 .shift = 16,
747 .data = &(struct clk_regmap_div_data){
749 .shift = 4,
764 .data = &(struct clk_regmap_mux_data){
767 .shift = 2,
782 .data = &(struct clk_regmap_div_data){
784 .shift = 20,
799 .data = &(struct clk_regmap_mux_data){
802 .shift = 18,
817 .data = &(struct clk_regmap_mux_data){
820 .shift = 10,
835 .data = &(struct clk_regmap_mux_data){
838 .shift = 11,
853 .data = &(struct clk_regmap_mux_data){
856 .shift = 24,
871 .data = &(struct clk_regmap_mux_data){
874 .shift = 25,
889 .data = &(struct clk_regmap_mux_data){
892 .shift = 26,
907 .data = &(struct clk_regmap_mux_data){
910 .shift = 27,
924 unsigned long event, void *data) in g12a_cpu_clk_mux_notifier_cb() argument
949 unsigned long event, void *data) in g12a_cpu_clk_postmux_notifier_cb() argument
960 * \- cpu_clk_dyn in g12a_cpu_clk_postmux_notifier_cb()
961 * \- cpu_clk_postmux0 in g12a_cpu_clk_postmux_notifier_cb()
962 * \- cpu_clk_muxX_div in g12a_cpu_clk_postmux_notifier_cb()
963 * \- cpu_clk_premux0 in g12a_cpu_clk_postmux_notifier_cb()
964 * \- fclk_div3 or fclk_div2 in g12a_cpu_clk_postmux_notifier_cb()
966 * \- cpu_clk_premux0 in g12a_cpu_clk_postmux_notifier_cb()
967 * \- fclk_div3 or fclk_div2 in g12a_cpu_clk_postmux_notifier_cb()
971 clk_hw_set_parent(nb_data->cpu_clk_premux1, in g12a_cpu_clk_postmux_notifier_cb()
972 nb_data->xtal); in g12a_cpu_clk_postmux_notifier_cb()
975 clk_hw_set_parent(nb_data->cpu_clk_postmux1, in g12a_cpu_clk_postmux_notifier_cb()
976 nb_data->cpu_clk_premux1); in g12a_cpu_clk_postmux_notifier_cb()
979 clk_hw_set_parent(nb_data->cpu_clk_dyn, in g12a_cpu_clk_postmux_notifier_cb()
980 nb_data->cpu_clk_postmux1); in g12a_cpu_clk_postmux_notifier_cb()
985 * \- cpu_clk_dyn in g12a_cpu_clk_postmux_notifier_cb()
986 * \- cpu_clk_postmux1 in g12a_cpu_clk_postmux_notifier_cb()
987 * \- cpu_clk_premux1 in g12a_cpu_clk_postmux_notifier_cb()
988 * \- xtal in g12a_cpu_clk_postmux_notifier_cb()
1003 clk_hw_set_parent(nb_data->cpu_clk_dyn, in g12a_cpu_clk_postmux_notifier_cb()
1004 nb_data->cpu_clk_postmux0); in g12a_cpu_clk_postmux_notifier_cb()
1009 * \- cpu_clk_dyn in g12a_cpu_clk_postmux_notifier_cb()
1010 * \- cpu_clk_postmux0 in g12a_cpu_clk_postmux_notifier_cb()
1011 * \- cpu_clk_muxX_div in g12a_cpu_clk_postmux_notifier_cb()
1012 * \- cpu_clk_premux0 in g12a_cpu_clk_postmux_notifier_cb()
1013 * \- fclk_div3 or fclk_div2 in g12a_cpu_clk_postmux_notifier_cb()
1015 * \- cpu_clk_premux0 in g12a_cpu_clk_postmux_notifier_cb()
1016 * \- fclk_div3 or fclk_div2 in g12a_cpu_clk_postmux_notifier_cb()
1052 unsigned long event, void *data) in g12a_sys_pll_notifier_cb() argument
1063 * \- sys_pll in g12a_sys_pll_notifier_cb()
1064 * \- sys_pll_dco in g12a_sys_pll_notifier_cb()
1068 clk_hw_set_parent(nb_data->cpu_clk, in g12a_sys_pll_notifier_cb()
1069 nb_data->cpu_clk_dyn); in g12a_sys_pll_notifier_cb()
1074 * \- cpu_clk_dyn in g12a_sys_pll_notifier_cb()
1075 * \- cpu_clk_dynX in g12a_sys_pll_notifier_cb()
1076 * \- cpu_clk_dynX_sel in g12a_sys_pll_notifier_cb()
1077 * \- cpu_clk_dynX_div in g12a_sys_pll_notifier_cb()
1078 * \- xtal/fclk_div2/fclk_div3 in g12a_sys_pll_notifier_cb()
1079 * \- xtal/fclk_div2/fclk_div3 in g12a_sys_pll_notifier_cb()
1093 clk_hw_set_parent(nb_data->cpu_clk, in g12a_sys_pll_notifier_cb()
1094 nb_data->sys_pll); in g12a_sys_pll_notifier_cb()
1100 * \- sys_pll in g12a_sys_pll_notifier_cb()
1101 * \- sys_pll_dco in g12a_sys_pll_notifier_cb()
1135 .data = &(struct clk_regmap_gate_data){
1154 .data = &(struct clk_regmap_gate_data){
1199 .data = &(struct clk_regmap_div_data){
1201 .shift = 3,
1214 .data = &(struct clk_regmap_gate_data){
1233 .data = &(struct clk_regmap_div_data){
1235 .shift = 6,
1248 .data = &(struct clk_regmap_gate_data){
1267 .data = &(struct clk_regmap_div_data){
1269 .shift = 9,
1282 .data = &(struct clk_regmap_gate_data){
1301 .data = &(struct clk_regmap_div_data){
1303 .shift = 20,
1319 .index = -1,
1326 .data = &(struct clk_regmap_gate_data){
1437 .data = &(struct clk_regmap_mux_data){
1440 .shift = 3,
1460 .data = &(struct clk_regmap_gate_data){
1480 .data = &(struct clk_regmap_mux_data){
1483 .shift = 6,
1503 .data = &(struct clk_regmap_gate_data){
1523 .data = &(struct clk_regmap_mux_data){
1526 .shift = 9,
1546 .data = &(struct clk_regmap_gate_data){
1566 .data = &(struct clk_regmap_mux_data){
1569 .shift = 20,
1589 .data = &(struct clk_regmap_gate_data){
1626 .data = &(struct meson_clk_pll_data){
1629 .shift = 28,
1634 .shift = 0,
1639 .shift = 10,
1644 .shift = 0,
1649 .shift = 31,
1654 .shift = 29,
1672 .data = &(struct clk_regmap_div_data){
1674 .shift = 16,
1691 .data = &(struct meson_clk_pll_data){
1694 .shift = 28,
1699 .shift = 0,
1704 .shift = 10,
1709 .shift = 0,
1714 .shift = 31,
1719 .shift = 29,
1736 .data = &(struct clk_regmap_div_data){
1738 .shift = 16,
1766 .data = &(struct meson_clk_pll_data){
1769 .shift = 28,
1774 .shift = 0,
1779 .shift = 10,
1784 .shift = 0,
1789 .shift = 31,
1794 .shift = 29,
1813 .data = &(struct clk_regmap_div_data){
1815 .shift = 16,
1858 .data = &(struct meson_clk_pll_data){
1861 .shift = 28,
1866 .shift = 0,
1871 .shift = 10,
1876 .shift = 0,
1881 .shift = 31,
1886 .shift = 29,
1918 .data = &(struct clk_regmap_div_data){
1920 .shift = 16,
1952 .data = &(struct meson_clk_pll_data){
1955 .shift = 28,
1960 .shift = 0,
1965 .shift = 10,
1970 .shift = 0,
1975 .shift = 30,
1980 .shift = 29,
2000 .data = &(struct clk_regmap_div_data){
2002 .shift = 16,
2018 .data = &(struct clk_regmap_div_data){
2020 .shift = 18,
2036 .data = &(struct clk_regmap_div_data){
2038 .shift = 20,
2065 .data = &(struct clk_regmap_gate_data){
2091 .data = &(struct clk_regmap_gate_data){
2117 .data = &(struct clk_regmap_gate_data){
2145 .data = &(struct clk_regmap_gate_data){
2173 .data = &(struct clk_regmap_mux_data){
2176 .shift = 5,
2207 .data = &(struct meson_clk_mpll_data){
2210 .shift = 0,
2215 .shift = 30,
2220 .shift = 20,
2225 .shift = 29,
2243 .data = &(struct clk_regmap_gate_data){
2261 .data = &(struct meson_clk_mpll_data){
2264 .shift = 0,
2269 .shift = 30,
2274 .shift = 20,
2279 .shift = 29,
2297 .data = &(struct clk_regmap_gate_data){
2315 .data = &(struct meson_clk_mpll_data){
2318 .shift = 0,
2323 .shift = 30,
2328 .shift = 20,
2333 .shift = 29,
2351 .data = &(struct clk_regmap_gate_data){
2369 .data = &(struct meson_clk_mpll_data){
2372 .shift = 0,
2377 .shift = 30,
2382 .shift = 20,
2387 .shift = 29,
2405 .data = &(struct clk_regmap_gate_data){
2430 .data = &(struct clk_regmap_mux_data){
2433 .shift = 12,
2445 .data = &(struct clk_regmap_div_data){
2447 .shift = 0,
2462 .data = &(struct clk_regmap_gate_data){
2493 .data = &(struct clk_regmap_mux_data){
2496 .shift = 9,
2508 .data = &(struct clk_regmap_div_data){
2510 .shift = 0,
2525 .data = &(struct clk_regmap_gate_data){
2542 .data = &(struct clk_regmap_mux_data){
2545 .shift = 25,
2557 .data = &(struct clk_regmap_div_data){
2559 .shift = 16,
2574 .data = &(struct clk_regmap_gate_data){
2591 .data = &(struct clk_regmap_mux_data){
2594 .shift = 9,
2606 .data = &(struct clk_regmap_div_data){
2608 .shift = 0,
2623 .data = &(struct clk_regmap_gate_data){
2641 .data = &(struct meson_vid_pll_div_data){
2644 .shift = 0,
2649 .shift = 16,
2668 .data = &(struct clk_regmap_mux_data){
2671 .shift = 18,
2687 .data = &(struct clk_regmap_gate_data){
2716 .data = &(struct clk_regmap_mux_data){
2719 .shift = 9,
2731 .data = &(struct clk_regmap_div_data){
2733 .shift = 0,
2746 .data = &(struct clk_regmap_gate_data){
2760 .data = &(struct clk_regmap_mux_data){
2763 .shift = 25,
2775 .data = &(struct clk_regmap_div_data){
2777 .shift = 16,
2790 .data = &(struct clk_regmap_gate_data){
2804 .data = &(struct clk_regmap_mux_data){
2807 .shift = 31,
2838 .data = &(struct clk_regmap_mux_data){
2841 .shift = 9,
2854 .data = &(struct clk_regmap_div_data){
2856 .shift = 0,
2872 .data = &(struct clk_regmap_gate_data){
2888 .data = &(struct clk_regmap_mux_data){
2891 .shift = 9,
2904 .data = &(struct clk_regmap_div_data){
2906 .shift = 0,
2922 .data = &(struct clk_regmap_gate_data){
2938 .data = &(struct clk_regmap_mux_data){
2941 .shift = 25,
2954 .data = &(struct clk_regmap_div_data){
2956 .shift = 16,
2972 .data = &(struct clk_regmap_gate_data){
3001 .data = &(struct clk_regmap_mux_data){
3004 .shift = 9,
3016 .data = &(struct clk_regmap_div_data){
3018 .shift = 0,
3033 .data = &(struct clk_regmap_gate_data){
3049 .data = &(struct clk_regmap_mux_data){
3052 .shift = 25,
3064 .data = &(struct clk_regmap_div_data){
3066 .shift = 16,
3081 .data = &(struct clk_regmap_gate_data){
3097 .data = &(struct clk_regmap_mux_data){
3100 .shift = 31,
3119 .data = &(struct clk_regmap_gate_data){
3144 .data = &(struct clk_regmap_mux_data){
3147 .shift = 16,
3159 .data = &(struct clk_regmap_mux_data){
3162 .shift = 16,
3174 .data = &(struct clk_regmap_gate_data){
3188 .data = &(struct clk_regmap_gate_data){
3201 .data = &(struct clk_regmap_div_data){
3203 .shift = 0,
3218 .data = &(struct meson_vclk_div_data){
3221 .shift = 0,
3226 .shift = 16,
3231 .shift = 17,
3248 .data = &(struct clk_regmap_gate_data){
3262 .data = &(struct meson_vclk_gate_data){
3265 .shift = 19,
3270 .shift = 15,
3284 .data = &(struct clk_regmap_gate_data){
3298 .data = &(struct clk_regmap_gate_data){
3312 .data = &(struct clk_regmap_gate_data){
3326 .data = &(struct clk_regmap_gate_data){
3340 .data = &(struct clk_regmap_gate_data){
3354 .data = &(struct clk_regmap_gate_data){
3368 .data = &(struct clk_regmap_gate_data){
3382 .data = &(struct clk_regmap_gate_data){
3396 .data = &(struct clk_regmap_gate_data){
3410 .data = &(struct clk_regmap_gate_data){
3546 .data = &(struct clk_regmap_mux_data){
3549 .shift = 28,
3562 .data = &(struct clk_regmap_mux_data){
3565 .shift = 20,
3578 .data = &(struct clk_regmap_mux_data){
3581 .shift = 12,
3594 .data = &(struct clk_regmap_mux_data){
3597 .shift = 28,
3625 .data = &(struct clk_regmap_mux_data){
3628 .shift = 16,
3641 .data = &(struct clk_regmap_gate_data){
3657 .data = &(struct clk_regmap_gate_data){
3673 .data = &(struct clk_regmap_gate_data){
3689 .data = &(struct clk_regmap_gate_data){
3705 .data = &(struct clk_regmap_gate_data){
3734 .data = &(struct clk_regmap_mux_data){
3737 .shift = 12,
3760 .data = &(struct clk_regmap_div_data){
3762 .shift = 0,
3778 .data = &(struct clk_regmap_gate_data){
3807 .data = &(struct clk_regmap_mux_data){
3810 .shift = 9,
3821 .data = &(struct clk_regmap_div_data){
3823 .shift = 0,
3838 .data = &(struct clk_regmap_gate_data){
3863 .data = &(struct clk_regmap_mux_data){
3866 .shift = 9,
3879 .data = &(struct clk_regmap_div_data){
3881 .shift = 0,
3894 .data = &(struct clk_regmap_gate_data){
3909 * muxed by a glitch-free switch. The CCF can manage this glitch-free
3910 * mux because it does top-to-bottom updates the each clock tree and
3925 .data = &(struct clk_regmap_mux_data){
3928 .shift = 9,
3946 .data = &(struct clk_regmap_div_data){
3948 .shift = 0,
3963 .data = &(struct clk_regmap_gate_data){
3979 .data = &(struct clk_regmap_mux_data){
3982 .shift = 25,
4000 .data = &(struct clk_regmap_div_data){
4002 .shift = 16,
4017 .data = &(struct clk_regmap_gate_data){
4038 .data = &(struct clk_regmap_mux_data){
4041 .shift = 31,
4053 .data = &(struct clk_regmap_div_data){
4055 .shift = 0,
4069 .data = &(struct clk_regmap_gate_data){
4095 .data = &(struct clk_regmap_mux_data){
4098 .shift = 7,
4109 .data = &(struct clk_regmap_div_data){
4111 .shift = 0,
4126 .data = &(struct clk_regmap_gate_data){
4142 .data = &(struct clk_regmap_mux_data){
4145 .shift = 23,
4156 .data = &(struct clk_regmap_div_data){
4158 .shift = 16,
4173 .data = &(struct clk_regmap_gate_data){
4202 .data = &(struct clk_regmap_mux_data){
4205 .shift = 9,
4216 .data = &(struct clk_regmap_div_data){
4218 .shift = 0,
4233 .data = &(struct clk_regmap_gate_data){
4249 .data = &(struct clk_regmap_mux_data){
4252 .shift = 25,
4263 .data = &(struct clk_regmap_div_data){
4265 .shift = 16,
4280 .data = &(struct clk_regmap_gate_data){
5419 struct device *dev = &pdev->dev; in meson_g12b_dvfs_setup()
5496 struct device *dev = &pdev->dev; in meson_g12a_dvfs_setup()
5536 eeclkc_data = of_device_get_match_data(&pdev->dev); in meson_g12a_probe()
5538 return -EINVAL; in meson_g12a_probe()
5547 if (g12a_data->dvfs_setup) in meson_g12a_probe()
5548 return g12a_data->dvfs_setup(pdev); in meson_g12a_probe()
5593 .compatible = "amlogic,g12a-clkc",
5594 .data = &g12a_clkc_data.eeclkc_data
5597 .compatible = "amlogic,g12b-clkc",
5598 .data = &g12b_clkc_data.eeclkc_data
5601 .compatible = "amlogic,sm1-clkc",
5602 .data = &sm1_clkc_data.eeclkc_data
5611 .name = "g12a-clkc",