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/linux-6.12.1/Documentation/devicetree/bindings/mmc/
Dsynopsys-dw-mshc-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: mmc-controller.yaml#
13 - Ulf Hansson <ulf.hansson@linaro.org>
20 reset-names:
23 clock-frequency:
29 fifo-depth:
31 The maximum size of the tx/rx fifo's. If this property is not
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Dsynopsys-dw-mshc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
16 - altr,socfpga-dw-mshc
17 - img,pistachio-dw-mshc
18 - snps,dw-mshc
33 clock-names:
35 - const: biu
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/linux-6.12.1/include/linux/amba/
Dpl022.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (C) 2008-2009 ST-Ericsson AB
11 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
31 * enum ssp_interface - interfaces allowed for this SSP Controller
48 * enum ssp_hierarchy - whether SSP is configured as Master or Slave
56 * enum ssp_clock_params - clock parameters, to set SSP clock at a
65 * enum ssp_rx_endian - endianess of Rx FIFO Data
74 * enum ssp_tx_endian - endianess of Tx FIFO Data
82 * enum ssp_data_size - number of bits in one data element
98 * enum ssp_mode - SSP mode of operation (Communication modes)
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/linux-6.12.1/Documentation/devicetree/bindings/spi/
Darm,pl022-peripheral-props.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/arm,pl022-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for Arm PL022 SPI controller
10 - Linus Walleij <linus.walleij@linaro.org>
19 - 0 # SPI
20 - 1 # Texas Instruments Synchronous Serial Frame Format
21 - 2 # Microwire (Half Duplex)
23 pl022,com-mode:
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/linux-6.12.1/drivers/tty/serial/
Dmsm_serial.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/dma-mapping.h>
169 } rx; member
198 writel_relaxed(val, port->membase + off); in msm_write()
204 return readl_relaxed(port->membase + off); in msm_read()
216 port->uartclk = 1843200; in msm_serial_set_mnd_regs_tcxo()
228 port->uartclk = 1843200; in msm_serial_set_mnd_regs_tcxoby4()
239 if (msm_port->is_uartdm) in msm_serial_set_mnd_regs()
242 if (port->uartclk == 19200000) in msm_serial_set_mnd_regs()
244 else if (port->uartclk == 4800000) in msm_serial_set_mnd_regs()
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Dsifive.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2018-2019 SiFive
8 * - drivers/tty/serial/pxa.c
9 * - drivers/tty/serial/amba-pl011.c
10 * - drivers/tty/serial/uartlite.c
11 * - drivers/tty/serial/omap-serial.c
12 * - drivers/pwm/pwm-sifive.c
15 * - Chapter 19 "Universal Asynchronous Receiver/Transmitter (UART)" of
16 * SiFive FE310-G000 v2p3
17 * - The tree/master/src/main/scala/devices/uart directory of
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/linux-6.12.1/drivers/spi/
Dspi-fsl-lpspi.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <linux/dma-mapping.h>
22 #include <linux/dma/imx-dma.h>
34 #define FSL_LPSPI_MAX_EDMA_BYTES ((1 << 15) - 1)
110 void (*rx)(struct fsl_lpspi_data *); member
113 u8 watermark; member
143 { .compatible = "fsl,imx7ulp-spi", .data = &imx7ulp_lpspi_devtype_data,},
144 { .compatible = "fsl,imx93-spi", .data = &imx93_lpspi_devtype_data,},
152 unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR); \
154 if (fsl_lpspi->rx_buf) { \
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Dspi-sifive.c1 // SPDX-License-Identifier: GPL-2.0
35 #define SIFIVE_SPI_REG_RXDATA 0x4c /* Rx FIFO data */
36 #define SIFIVE_SPI_REG_TXMARK 0x50 /* Tx FIFO watermark */
37 #define SIFIVE_SPI_REG_RXMARK 0x54 /* Rx FIFO watermark */
96 struct completion done; /* wake-up from interrupt */
101 iowrite32(value, spi->regs + offset); in sifive_spi_write()
106 return ioread32(spi->regs + offset); in sifive_spi_read()
111 /* Watermark interrupts are disabled by default */ in sifive_spi_init()
114 /* Default watermark FIFO threshold values */ in sifive_spi_init()
126 /* Exit specialized memory-mapped SPI flash mode */ in sifive_spi_init()
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/linux-6.12.1/Documentation/devicetree/bindings/net/
Dcdns,macb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Claudiu Beznea <claudiu.beznea@microchip.com>
16 - items:
17 - enum:
18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC
19 - const: cdns,emac # Generic
21 - items:
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/linux-6.12.1/Documentation/networking/device_drivers/ethernet/toshiba/
Dspider_net.rst1 .. SPDX-License-Identifier: GPL-2.0
18 The Structure of the RX Ring.
20 The receive (RX) ring is a circular linked list of RX descriptors,
29 "full" and "not-in-use". An "empty" or "ready" descriptor is ready
31 and is waiting to be emptied and processed by the OS. A "not-in-use"
36 spidernet device driver) allocates a set of RX descriptors and RX
40 buffers, processing them, and re-marking them empty.
47 flowing RX traffic, every descr behind it should be marked "full",
54 descr. The OS will process this descr, and then mark it "not-in-use",
55 and advance the tail pointer. Thus, when there is flowing RX traffic,
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/linux-6.12.1/Documentation/trace/
Dhisi-ptt.rst1 .. SPDX-License-Identifier: GPL-2.0
23 +--------------Core 0-------+
25 | | [Root Port]---[Endpoint]
26 | | [Root Port]---[Endpoint]
27 | | [Root Port]---[Endpoint]
28 Root Complex |------Core 1-------+
30 | | [Root Port]---[ Switch ]---[Endpoint]
31 | | [Root Port]---[Endpoint] `-[Endpoint]
32 | | [Root Port]---[Endpoint]
33 +---------------------------+
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/linux-6.12.1/arch/arm/mach-omap1/
Dserial.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-omap1/serial.c
21 #include <asm/mach-types.h>
36 offset <<= up->regshift; in omap_serial_in()
37 return (unsigned int)__raw_readb(up->membase + offset); in omap_serial_in()
43 offset <<= p->regshift; in omap_serial_outp()
44 __raw_writeb(value, p->membase + offset); in omap_serial_outp()
49 * properly. Note that the TX watermark initialization may not be needed
50 * once the 8250.c watermark handling code is merged.
56 omap_serial_outp(p, UART_OMAP_SCR, 0x08); /* TX watermark */ in omap_serial_reset()
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/linux-6.12.1/drivers/net/ethernet/microchip/sparx5/
Dsparx5_fdma.c1 // SPDX-License-Identifier: GPL-2.0+
7 * https://github.com/microchip-ung/sparx-5_reginfo
15 #include <linux/dma-mapping.h>
30 *dataptr = fdma->dma + (sizeof(struct fdma_dcb) * fdma->n_dcbs) + in sparx5_fdma_tx_dataptr_cb()
31 ((dcb * fdma->n_dbs + db) * fdma->db_size); in sparx5_fdma_tx_dataptr_cb()
39 struct sparx5 *sparx5 = fdma->priv; in sparx5_fdma_rx_dataptr_cb()
40 struct sparx5_rx *rx = &sparx5->rx; in sparx5_fdma_rx_dataptr_cb() local
43 skb = __netdev_alloc_skb(rx->ndev, fdma->db_size, GFP_ATOMIC); in sparx5_fdma_rx_dataptr_cb()
45 return -ENOMEM; in sparx5_fdma_rx_dataptr_cb()
47 *dataptr = virt_to_phys(skb->data); in sparx5_fdma_rx_dataptr_cb()
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/linux-6.12.1/sound/pci/ice1712/
Denvy24ht.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
39 #define ICEREG1724(ice, x) ((ice)->port + VT1724_REG_##x)
49 #define VT1724_REG_SYS_CFG 0x04 /* byte - system configuration PCI60 on Envy24*/
60 #define VT1724_CFG_AC97_PACKED 0x01 /* split or packed mode - AC'97 */
65 #define VT1724_CFG_I2S_RESMASK 0x30 /* resolution mask, 16,18,20,24-bit */
81 #define VT1724_REG_MPU_RXFIFO 0x0b /*byte ro. number of bytes in RX fifo*/
91 #define VT1724_REG_MPU_FIFO_WM 0x0e /*byte set the high/low watermarks for RX/TX fifos*/
92 #define VT1724_MPU_RX_FIFO 0x20 //1=rx fifo watermark 0=tx fifo watermark
106 bit3 - during reset used for Eeprom power-on strapping
114 * Professional multi-track direct control registers
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/linux-6.12.1/drivers/net/ethernet/sun/
Dsunqe.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define GLOB_MSIZE 0x0cUL /* Local-memory Size */
45 /* The following registers are for per-qe channel information/status. */
48 #define CREG_RXDS 0x08UL /* RX descriptor ring ptr */
50 #define CREG_RIMASK 0x10UL /* RX Interrupt Mask */
54 #define CREG_RXWBUFPTR 0x20UL /* Local memory rx write ptr */
55 #define CREG_RXRBUFPTR 0x24UL /* Local memory rx read ptr */
59 #define CREG_PIPG 0x34UL /* Inter-Frame Gap */
74 #define CREG_STAT_CCOFLOW 0x00100000 /* TX Coll-counter Overflow */
79 #define CREG_STAT_RCCOFLOW 0x00001000 /* RX Coll-counter Overflow */
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/linux-6.12.1/Documentation/hid/
Dintel-ish-hid.rst6 processing to a dedicated low power co-processor. This allows the core
11 Sensor usage tables. These may be found in tablets, 2-in-1 convertible laptops
27 ----------------- ----------------------
28 | USB HID | --> | ISH HID |
29 ----------------- ----------------------
30 ----------------- ----------------------
31 | USB protocol | --> | ISH Transport |
32 ----------------- ----------------------
33 ----------------- ----------------------
34 | EHCI/XHCI | --> | ISH IPC |
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/linux-6.12.1/drivers/net/ethernet/marvell/octeon_ep_vf/
Doctep_vf_config.h1 /* SPDX-License-Identifier: GPL-2.0 */
22 /* Minimum watermark for backpressure */
25 /* Rx Queue: maximum descriptors per ring */
28 /* Rx buffer size: Use page size buffers.
31 * page buffers in consecutive Rx descriptors as fragments.
51 #define OCTEP_VF_MAX_MTU (10000 - (ETH_HLEN + ETH_FCS_LEN))
56 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq)
57 #define CFG_GET_IQ_NUM_DESC(cfg) ((cfg)->iq.num_descs)
58 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type)
60 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min)
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/linux-6.12.1/drivers/media/i2c/cx25840/
Dcx25840-ir.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <media/drv-intf/cx25840.h>
14 #include <media/rc-core.h>
16 #include "cx25840-core.h"
102 struct mutex rx_params_lock; /* protects Rx parameter settings cache */
107 spinlock_t rx_kfifo_lock; /* protect Rx data kfifo */
117 return state ? state->ir_state : NULL; in to_ir_state()
122 * Rx and Tx Clock Divider register computations
135 d--; in count_to_clock_divider()
265 * Pulse Clocks computations: Combined Pulse Width Count & Rx Clock Counts
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/linux-6.12.1/drivers/net/usb/
Dsmsc95xx.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 2007-2008 SMSC
22 /* Rx status word */
38 /* SCSRs - System Control and Status Registers */
54 #define INT_STS_RX_STOP_ (0x00010000) /* RX Stopped */
59 #define INT_STS_RXDF_ (0x00000800) /* RX Dropped Frame */
77 #define HW_CFG_RXDOFF_ (0x00000600) /* RX Data Offset */
80 #define HW_CFG_DRP_ (0x00000040) /* Discard Errored RX Frame */
90 #define RX_FIFO_INF_USED_ (0x0000FFFF) /* RX Data FIFO Used Space */
133 /* Hi watermark = 15.5Kb (~10 mtu pkts) */
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/linux-6.12.1/drivers/media/pci/cx23885/
Dcx23888-ir.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include "cx23888-ir.h"
16 #include <media/v4l2-device.h>
17 #include <media/rc-core.h>
161 * Rx and Tx Clock Divider register computations
174 d--; in count_to_clock_divider()
278 * Pulse Clocks computations: Combined Pulse Width Count & Rx Clock Counts
282 * When the Rx clock divider ticks down to 0, it increments the 18 bit pulse
306 count--; in pulse_clocks_to_clock_divider()
384 if (*carrier_range_high > DIV_ROUND_CLOSEST(c16, 16 - 3)) { in control_rx_s_carrier_window()
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/linux-6.12.1/sound/soc/fsl/
Dfsl_sai.c1 // SPDX-License-Identifier: GPL-2.0+
5 // Copyright 2012-2015 Freescale Semiconductor, Inc.
22 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
26 #include "imx-pcm.h"
44 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream
55 int adir = (dir == TX) ? RX : TX; in fsl_sai_dir_is_synced()
58 return !sai->synchronous[dir] && sai->synchronous[adir]; in fsl_sai_dir_is_synced()
65 if (sai->is_pdm_mode) { in fsl_sai_get_pins_state()
68 state = pinctrl_lookup_state(sai->pinctrl, "dsd512"); in fsl_sai_get_pins_state()
72 state = pinctrl_lookup_state(sai->pinctrl, "dsd"); in fsl_sai_get_pins_state()
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/linux-6.12.1/include/uapi/linux/
Dserial_reg.h1 /* SPDX-License-Identifier: GPL-1.0+ WITH Linux-syscall-note */
44 #define UART_IIR_RX_TIMEOUT 0x0c /* OMAP RX Timeout interrupt */
61 * RX:76 = 00 01 10 11 TX:54 = 00 01 10 11
132 #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
142 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
200 #define UART_TRG 0 /* FCTR bit 7 selects Rx or Tx
223 #define UART_FCTR_TRGA 0x00 /* Tx/Rx 550 trigger table select */
224 #define UART_FCTR_TRGB 0x10 /* Tx/Rx 650 trigger table select */
225 #define UART_FCTR_TRGC 0x20 /* Tx/Rx 654 trigger table select */
226 #define UART_FCTR_TRGD 0x30 /* Tx/Rx 850 programmable trigger select */
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/linux-6.12.1/drivers/net/ethernet/marvell/octeon_ep/
Doctep_config.h1 /* SPDX-License-Identifier: GPL-2.0 */
23 /* Minimum watermark for backpressure */
26 /* Rx Queue: maximum descriptors per ring */
29 /* Rx buffer size: Use page size buffers.
32 * page buffers in consecutive Rx descriptors as fragments.
60 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq)
61 #define CFG_GET_IQ_NUM_DESC(cfg) ((cfg)->iq.num_descs)
62 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type)
64 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min)
65 #define CFG_GET_IQ_INTR_THRESHOLD(cfg) ((cfg)->iq.intr_threshold)
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/linux-6.12.1/drivers/net/ethernet/atheros/atlx/
Datl2.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* atl2.h -- atl2 driver definitions
9 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
39 ((a)->hw_addr + (reg))))
41 #define ATL2_WRITE_FLUSH(a) (ioread32((a)->hw_addr))
43 #define ATL2_READ_REG(a, reg) (ioread32((a)->hw_addr + (reg)))
46 ((a)->hw_addr + (reg))))
48 #define ATL2_READ_REGB(a, reg) (ioread8((a)->hw_addr + (reg)))
51 ((a)->hw_addr + (reg))))
53 #define ATL2_READ_REGW(a, reg) (ioread16((a)->hw_addr + (reg)))
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/linux-6.12.1/drivers/soc/qcom/
Dqcom-geni-se.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
10 #include <linux/dma-mapping.h>
17 #include <linux/soc/qcom/geni-se.h>
31 * GENI based QUP is a highly-flexible and programmable module for supporting
41 * +-----------------------------------------+
43 * | +----------------------------+ |
44 * --QUP & SE Clocks--> | Serial Engine N | +-IO------>
46 * <---Clock Perf.----+ +----+-----------------------+ | |
50 * <--------AHB-------> | | | |
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