uapi/linux/serial_reg.h

1 /* SPDX-License-Identifier: GPL-1.0+ WITH Linux-syscall-note */
44 #define UART_IIR_RX_TIMEOUT	0x0c /* OMAP RX Timeout interrupt */
61  *	RX:76 = 00  01  10  11	TX:54 = 00  01  10  11
132 #define UART_MCR_AFE		0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
142 #define UART_LSR_THRE		0x20 /* Transmit-hold-register empty */
200 #define UART_TRG	0	/* FCTR bit 7 selects Rx or Tx
223 #define UART_FCTR_TRGA		0x00  /* Tx/Rx 550 trigger table select */
224 #define UART_FCTR_TRGB		0x10  /* Tx/Rx 650 trigger table select */
225 #define UART_FCTR_TRGC		0x20  /* Tx/Rx 654 trigger table select */
226 #define UART_FCTR_TRGD		0x30  /* Tx/Rx 850 programmable trigger select */
235 #define UART_EMSR_FIFO_COUNT	0x01  /* Rx/Tx select */
239  * The Intel XScale on-chip UARTs define these bits
275 #define UART_NMR	0x0D	/* Nine-bit Mode Register */
291  * These definitions are for the RSA-DV II/S card, from
293  * Kiyokazu SUTO <suto@ks-and-ks.ne.jp>
296 #define UART_RSA_BASE (-8)
307 #define UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */
318 #define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3) /* Rx FIFO is not empty (1) */
319 #define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */
320 #define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5) /* Rx FIFO is not full (1) */
343 #define UART_DA830_PWREMU_MGMT_FREE	(1 << 0)  /* Free-running mode */
363 #define UART_OMAP_WER		0x17	/* Wake-up enable register */
371 #define UART_OMAP_MDR1_16X_ABAUD_MODE	0x02	/* UART 16x auto-baud */
383 #define UART_ALTR_EN_TXFIFO_LW	0x01	/* Enable the TX FIFO Low Watermark */
384 #define UART_ALTR_TX_LOW	0x41	/* Tx FIFO Low Watermark */