Lines Matching +full:rx +full:- +full:watermark
1 // SPDX-License-Identifier: GPL-2.0+
12 #include <linux/dma-mapping.h>
22 #include <linux/dma/imx-dma.h>
34 #define FSL_LPSPI_MAX_EDMA_BYTES ((1 << 15) - 1)
110 void (*rx)(struct fsl_lpspi_data *); member
113 u8 watermark; member
143 { .compatible = "fsl,imx7ulp-spi", .data = &imx7ulp_lpspi_devtype_data,},
144 { .compatible = "fsl,imx93-spi", .data = &imx93_lpspi_devtype_data,},
152 unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR); \
154 if (fsl_lpspi->rx_buf) { \
155 *(type *)fsl_lpspi->rx_buf = val; \
156 fsl_lpspi->rx_buf += sizeof(type); \
165 if (fsl_lpspi->tx_buf) { \
166 val = *(type *)fsl_lpspi->tx_buf; \
167 fsl_lpspi->tx_buf += sizeof(type); \
170 fsl_lpspi->remain -= sizeof(type); \
171 writel(val, fsl_lpspi->base + IMX7ULP_TDR); \
184 writel(enable, fsl_lpspi->base + IMX7ULP_IER); in LPSPI_BUF_TX()
198 if (!controller->dma_rx) in fsl_lpspi_can_dma()
201 bytes_per_word = fsl_lpspi_bytes_per_word(transfer->bits_per_word); in fsl_lpspi_can_dma()
221 ret = pm_runtime_resume_and_get(fsl_lpspi->dev); in lpspi_prepare_xfer_hardware()
223 dev_err(fsl_lpspi->dev, "failed to enable clock\n"); in lpspi_prepare_xfer_hardware()
235 pm_runtime_mark_last_busy(fsl_lpspi->dev); in lpspi_unprepare_xfer_hardware()
236 pm_runtime_put_autosuspend(fsl_lpspi->dev); in lpspi_unprepare_xfer_hardware()
246 txfifo_cnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff; in fsl_lpspi_write_tx_fifo()
248 while (txfifo_cnt < fsl_lpspi->txfifosize) { in fsl_lpspi_write_tx_fifo()
249 if (!fsl_lpspi->remain) in fsl_lpspi_write_tx_fifo()
251 fsl_lpspi->tx(fsl_lpspi); in fsl_lpspi_write_tx_fifo()
255 if (txfifo_cnt < fsl_lpspi->txfifosize) { in fsl_lpspi_write_tx_fifo()
256 if (!fsl_lpspi->is_target) { in fsl_lpspi_write_tx_fifo()
257 temp = readl(fsl_lpspi->base + IMX7ULP_TCR); in fsl_lpspi_write_tx_fifo()
259 writel(temp, fsl_lpspi->base + IMX7ULP_TCR); in fsl_lpspi_write_tx_fifo()
269 while (!(readl(fsl_lpspi->base + IMX7ULP_RSR) & RSR_RXEMPTY)) in fsl_lpspi_read_rx_fifo()
270 fsl_lpspi->rx(fsl_lpspi); in fsl_lpspi_read_rx_fifo()
277 temp |= fsl_lpspi->config.bpw - 1; in fsl_lpspi_set_cmd()
278 temp |= (fsl_lpspi->config.mode & 0x3) << 30; in fsl_lpspi_set_cmd()
279 temp |= (fsl_lpspi->config.chip_select & 0x3) << 24; in fsl_lpspi_set_cmd()
280 if (!fsl_lpspi->is_target) { in fsl_lpspi_set_cmd()
281 temp |= fsl_lpspi->config.prescale << 27; in fsl_lpspi_set_cmd()
287 if (!fsl_lpspi->usedma) { in fsl_lpspi_set_cmd()
289 if (fsl_lpspi->is_first_byte) in fsl_lpspi_set_cmd()
295 writel(temp, fsl_lpspi->base + IMX7ULP_TCR); in fsl_lpspi_set_cmd()
297 dev_dbg(fsl_lpspi->dev, "TCR=0x%x\n", temp); in fsl_lpspi_set_cmd()
304 if (!fsl_lpspi->usedma) in fsl_lpspi_set_watermark()
305 temp = fsl_lpspi->watermark >> 1 | in fsl_lpspi_set_watermark()
306 (fsl_lpspi->watermark >> 1) << 16; in fsl_lpspi_set_watermark()
308 temp = fsl_lpspi->watermark >> 1; in fsl_lpspi_set_watermark()
310 writel(temp, fsl_lpspi->base + IMX7ULP_FCR); in fsl_lpspi_set_watermark()
312 dev_dbg(fsl_lpspi->dev, "FCR=0x%x\n", temp); in fsl_lpspi_set_watermark()
317 struct lpspi_config config = fsl_lpspi->config; in fsl_lpspi_set_bitrate()
322 perclk_rate = clk_get_rate(fsl_lpspi->clk_per); in fsl_lpspi_set_bitrate()
323 prescale_max = fsl_lpspi->devtype_data->prescale_max; in fsl_lpspi_set_bitrate()
326 dev_err(fsl_lpspi->dev, in fsl_lpspi_set_bitrate()
328 return -EINVAL; in fsl_lpspi_set_bitrate()
332 dev_err(fsl_lpspi->dev, in fsl_lpspi_set_bitrate()
333 "per-clk should be at least two times of transfer speed"); in fsl_lpspi_set_bitrate()
334 return -EINVAL; in fsl_lpspi_set_bitrate()
340 scldiv = div / (1 << prescale) - 2; in fsl_lpspi_set_bitrate()
342 fsl_lpspi->config.prescale = prescale; in fsl_lpspi_set_bitrate()
348 return -EINVAL; in fsl_lpspi_set_bitrate()
351 fsl_lpspi->base + IMX7ULP_CCR); in fsl_lpspi_set_bitrate()
353 dev_dbg(fsl_lpspi->dev, "perclk=%d, speed=%d, prescale=%d, scldiv=%d\n", in fsl_lpspi_set_bitrate()
363 struct dma_slave_config rx = {}, tx = {}; in fsl_lpspi_dma_configure() local
367 switch (fsl_lpspi_bytes_per_word(fsl_lpspi->config.bpw)) { in fsl_lpspi_dma_configure()
378 return -EINVAL; in fsl_lpspi_dma_configure()
382 tx.dst_addr = fsl_lpspi->base_phys + IMX7ULP_TDR; in fsl_lpspi_dma_configure()
385 ret = dmaengine_slave_config(controller->dma_tx, &tx); in fsl_lpspi_dma_configure()
387 dev_err(fsl_lpspi->dev, "TX dma configuration failed with %d\n", in fsl_lpspi_dma_configure()
392 rx.direction = DMA_DEV_TO_MEM; in fsl_lpspi_dma_configure()
393 rx.src_addr = fsl_lpspi->base_phys + IMX7ULP_RDR; in fsl_lpspi_dma_configure()
394 rx.src_addr_width = buswidth; in fsl_lpspi_dma_configure()
395 rx.src_maxburst = 1; in fsl_lpspi_dma_configure()
396 ret = dmaengine_slave_config(controller->dma_rx, &rx); in fsl_lpspi_dma_configure()
398 dev_err(fsl_lpspi->dev, "RX dma configuration failed with %d\n", in fsl_lpspi_dma_configure()
411 if (!fsl_lpspi->is_target) { in fsl_lpspi_config()
419 if (!fsl_lpspi->is_target) in fsl_lpspi_config()
423 if (fsl_lpspi->config.mode & SPI_CS_HIGH) in fsl_lpspi_config()
425 writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1); in fsl_lpspi_config()
427 temp = readl(fsl_lpspi->base + IMX7ULP_CR); in fsl_lpspi_config()
429 writel(temp, fsl_lpspi->base + IMX7ULP_CR); in fsl_lpspi_config()
432 if (fsl_lpspi->usedma) in fsl_lpspi_config()
434 writel(temp, fsl_lpspi->base + IMX7ULP_DER); in fsl_lpspi_config()
444 spi_controller_get_devdata(spi->controller); in fsl_lpspi_setup_transfer()
447 return -EINVAL; in fsl_lpspi_setup_transfer()
449 fsl_lpspi->config.mode = spi->mode; in fsl_lpspi_setup_transfer()
450 fsl_lpspi->config.bpw = t->bits_per_word; in fsl_lpspi_setup_transfer()
451 fsl_lpspi->config.speed_hz = t->speed_hz; in fsl_lpspi_setup_transfer()
452 if (fsl_lpspi->is_only_cs1) in fsl_lpspi_setup_transfer()
453 fsl_lpspi->config.chip_select = 1; in fsl_lpspi_setup_transfer()
455 fsl_lpspi->config.chip_select = spi_get_chipselect(spi, 0); in fsl_lpspi_setup_transfer()
457 if (!fsl_lpspi->config.speed_hz) in fsl_lpspi_setup_transfer()
458 fsl_lpspi->config.speed_hz = spi->max_speed_hz; in fsl_lpspi_setup_transfer()
459 if (!fsl_lpspi->config.bpw) in fsl_lpspi_setup_transfer()
460 fsl_lpspi->config.bpw = spi->bits_per_word; in fsl_lpspi_setup_transfer()
463 if (fsl_lpspi->config.bpw <= 8) { in fsl_lpspi_setup_transfer()
464 fsl_lpspi->rx = fsl_lpspi_buf_rx_u8; in fsl_lpspi_setup_transfer()
465 fsl_lpspi->tx = fsl_lpspi_buf_tx_u8; in fsl_lpspi_setup_transfer()
466 } else if (fsl_lpspi->config.bpw <= 16) { in fsl_lpspi_setup_transfer()
467 fsl_lpspi->rx = fsl_lpspi_buf_rx_u16; in fsl_lpspi_setup_transfer()
468 fsl_lpspi->tx = fsl_lpspi_buf_tx_u16; in fsl_lpspi_setup_transfer()
470 fsl_lpspi->rx = fsl_lpspi_buf_rx_u32; in fsl_lpspi_setup_transfer()
471 fsl_lpspi->tx = fsl_lpspi_buf_tx_u32; in fsl_lpspi_setup_transfer()
474 if (t->len <= fsl_lpspi->txfifosize) in fsl_lpspi_setup_transfer()
475 fsl_lpspi->watermark = t->len; in fsl_lpspi_setup_transfer()
477 fsl_lpspi->watermark = fsl_lpspi->txfifosize; in fsl_lpspi_setup_transfer()
480 fsl_lpspi->usedma = true; in fsl_lpspi_setup_transfer()
482 fsl_lpspi->usedma = false; in fsl_lpspi_setup_transfer()
492 fsl_lpspi->target_aborted = true; in fsl_lpspi_target_abort()
493 if (!fsl_lpspi->usedma) in fsl_lpspi_target_abort()
494 complete(&fsl_lpspi->xfer_done); in fsl_lpspi_target_abort()
496 complete(&fsl_lpspi->dma_tx_completion); in fsl_lpspi_target_abort()
497 complete(&fsl_lpspi->dma_rx_completion); in fsl_lpspi_target_abort()
508 if (fsl_lpspi->is_target) { in fsl_lpspi_wait_for_completion()
509 if (wait_for_completion_interruptible(&fsl_lpspi->xfer_done) || in fsl_lpspi_wait_for_completion()
510 fsl_lpspi->target_aborted) { in fsl_lpspi_wait_for_completion()
511 dev_dbg(fsl_lpspi->dev, "interrupted\n"); in fsl_lpspi_wait_for_completion()
512 return -EINTR; in fsl_lpspi_wait_for_completion()
515 if (!wait_for_completion_timeout(&fsl_lpspi->xfer_done, HZ)) { in fsl_lpspi_wait_for_completion()
516 dev_dbg(fsl_lpspi->dev, "wait for completion timeout\n"); in fsl_lpspi_wait_for_completion()
517 return -ETIMEDOUT; in fsl_lpspi_wait_for_completion()
528 if (!fsl_lpspi->usedma) { in fsl_lpspi_reset()
535 writel(temp, fsl_lpspi->base + IMX7ULP_SR); in fsl_lpspi_reset()
539 writel(temp, fsl_lpspi->base + IMX7ULP_CR); in fsl_lpspi_reset()
548 complete(&fsl_lpspi->dma_rx_completion); in fsl_lpspi_dma_rx_callback()
555 complete(&fsl_lpspi->dma_tx_completion); in fsl_lpspi_dma_tx_callback()
564 timeout = (8 + 4) * size / fsl_lpspi->config.speed_hz; in fsl_lpspi_calculate_timeout()
580 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg; in fsl_lpspi_dma_transfer() local
587 desc_rx = dmaengine_prep_slave_sg(controller->dma_rx, in fsl_lpspi_dma_transfer()
588 rx->sgl, rx->nents, DMA_DEV_TO_MEM, in fsl_lpspi_dma_transfer()
591 return -EINVAL; in fsl_lpspi_dma_transfer()
593 desc_rx->callback = fsl_lpspi_dma_rx_callback; in fsl_lpspi_dma_transfer()
594 desc_rx->callback_param = (void *)fsl_lpspi; in fsl_lpspi_dma_transfer()
596 reinit_completion(&fsl_lpspi->dma_rx_completion); in fsl_lpspi_dma_transfer()
597 dma_async_issue_pending(controller->dma_rx); in fsl_lpspi_dma_transfer()
599 desc_tx = dmaengine_prep_slave_sg(controller->dma_tx, in fsl_lpspi_dma_transfer()
600 tx->sgl, tx->nents, DMA_MEM_TO_DEV, in fsl_lpspi_dma_transfer()
603 dmaengine_terminate_all(controller->dma_tx); in fsl_lpspi_dma_transfer()
604 return -EINVAL; in fsl_lpspi_dma_transfer()
607 desc_tx->callback = fsl_lpspi_dma_tx_callback; in fsl_lpspi_dma_transfer()
608 desc_tx->callback_param = (void *)fsl_lpspi; in fsl_lpspi_dma_transfer()
610 reinit_completion(&fsl_lpspi->dma_tx_completion); in fsl_lpspi_dma_transfer()
611 dma_async_issue_pending(controller->dma_tx); in fsl_lpspi_dma_transfer()
613 fsl_lpspi->target_aborted = false; in fsl_lpspi_dma_transfer()
615 if (!fsl_lpspi->is_target) { in fsl_lpspi_dma_transfer()
617 transfer->len); in fsl_lpspi_dma_transfer()
620 time_left = wait_for_completion_timeout(&fsl_lpspi->dma_tx_completion, in fsl_lpspi_dma_transfer()
623 dev_err(fsl_lpspi->dev, "I/O Error in DMA TX\n"); in fsl_lpspi_dma_transfer()
624 dmaengine_terminate_all(controller->dma_tx); in fsl_lpspi_dma_transfer()
625 dmaengine_terminate_all(controller->dma_rx); in fsl_lpspi_dma_transfer()
627 return -ETIMEDOUT; in fsl_lpspi_dma_transfer()
630 time_left = wait_for_completion_timeout(&fsl_lpspi->dma_rx_completion, in fsl_lpspi_dma_transfer()
633 dev_err(fsl_lpspi->dev, "I/O Error in DMA RX\n"); in fsl_lpspi_dma_transfer()
634 dmaengine_terminate_all(controller->dma_tx); in fsl_lpspi_dma_transfer()
635 dmaengine_terminate_all(controller->dma_rx); in fsl_lpspi_dma_transfer()
637 return -ETIMEDOUT; in fsl_lpspi_dma_transfer()
640 if (wait_for_completion_interruptible(&fsl_lpspi->dma_tx_completion) || in fsl_lpspi_dma_transfer()
641 fsl_lpspi->target_aborted) { in fsl_lpspi_dma_transfer()
642 dev_dbg(fsl_lpspi->dev, in fsl_lpspi_dma_transfer()
644 dmaengine_terminate_all(controller->dma_tx); in fsl_lpspi_dma_transfer()
645 dmaengine_terminate_all(controller->dma_rx); in fsl_lpspi_dma_transfer()
647 return -EINTR; in fsl_lpspi_dma_transfer()
650 if (wait_for_completion_interruptible(&fsl_lpspi->dma_rx_completion) || in fsl_lpspi_dma_transfer()
651 fsl_lpspi->target_aborted) { in fsl_lpspi_dma_transfer()
652 dev_dbg(fsl_lpspi->dev, in fsl_lpspi_dma_transfer()
653 "I/O Error in DMA RX interrupted\n"); in fsl_lpspi_dma_transfer()
654 dmaengine_terminate_all(controller->dma_tx); in fsl_lpspi_dma_transfer()
655 dmaengine_terminate_all(controller->dma_rx); in fsl_lpspi_dma_transfer()
657 return -EINTR; in fsl_lpspi_dma_transfer()
668 if (controller->dma_rx) { in fsl_lpspi_dma_exit()
669 dma_release_channel(controller->dma_rx); in fsl_lpspi_dma_exit()
670 controller->dma_rx = NULL; in fsl_lpspi_dma_exit()
673 if (controller->dma_tx) { in fsl_lpspi_dma_exit()
674 dma_release_channel(controller->dma_tx); in fsl_lpspi_dma_exit()
675 controller->dma_tx = NULL; in fsl_lpspi_dma_exit()
686 controller->dma_tx = dma_request_chan(dev, "tx"); in fsl_lpspi_dma_init()
687 if (IS_ERR(controller->dma_tx)) { in fsl_lpspi_dma_init()
688 ret = PTR_ERR(controller->dma_tx); in fsl_lpspi_dma_init()
690 controller->dma_tx = NULL; in fsl_lpspi_dma_init()
694 /* Prepare for RX DMA: */ in fsl_lpspi_dma_init()
695 controller->dma_rx = dma_request_chan(dev, "rx"); in fsl_lpspi_dma_init()
696 if (IS_ERR(controller->dma_rx)) { in fsl_lpspi_dma_init()
697 ret = PTR_ERR(controller->dma_rx); in fsl_lpspi_dma_init()
698 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret); in fsl_lpspi_dma_init()
699 controller->dma_rx = NULL; in fsl_lpspi_dma_init()
703 init_completion(&fsl_lpspi->dma_rx_completion); in fsl_lpspi_dma_init()
704 init_completion(&fsl_lpspi->dma_tx_completion); in fsl_lpspi_dma_init()
705 controller->can_dma = fsl_lpspi_can_dma; in fsl_lpspi_dma_init()
706 controller->max_dma_len = FSL_LPSPI_MAX_EDMA_BYTES; in fsl_lpspi_dma_init()
721 fsl_lpspi->tx_buf = t->tx_buf; in fsl_lpspi_pio_transfer()
722 fsl_lpspi->rx_buf = t->rx_buf; in fsl_lpspi_pio_transfer()
723 fsl_lpspi->remain = t->len; in fsl_lpspi_pio_transfer()
725 reinit_completion(&fsl_lpspi->xfer_done); in fsl_lpspi_pio_transfer()
726 fsl_lpspi->target_aborted = false; in fsl_lpspi_pio_transfer()
747 fsl_lpspi->is_first_byte = true; in fsl_lpspi_transfer_one()
753 fsl_lpspi->is_first_byte = false; in fsl_lpspi_transfer_one()
755 if (fsl_lpspi->usedma) in fsl_lpspi_transfer_one()
770 temp_IER = readl(fsl_lpspi->base + IMX7ULP_IER); in fsl_lpspi_isr()
772 temp_SR = readl(fsl_lpspi->base + IMX7ULP_SR); in fsl_lpspi_isr()
782 readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_TXCOUNT) { in fsl_lpspi_isr()
783 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR); in fsl_lpspi_isr()
789 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR); in fsl_lpspi_isr()
790 complete(&fsl_lpspi->xfer_done); in fsl_lpspi_isr()
806 ret = clk_prepare_enable(fsl_lpspi->clk_per); in fsl_lpspi_runtime_resume()
810 ret = clk_prepare_enable(fsl_lpspi->clk_ipg); in fsl_lpspi_runtime_resume()
812 clk_disable_unprepare(fsl_lpspi->clk_per); in fsl_lpspi_runtime_resume()
826 clk_disable_unprepare(fsl_lpspi->clk_per); in fsl_lpspi_runtime_suspend()
827 clk_disable_unprepare(fsl_lpspi->clk_ipg); in fsl_lpspi_runtime_suspend()
835 struct device *dev = fsl_lpspi->dev; in fsl_lpspi_init_rpm()
855 devtype_data = of_device_get_match_data(&pdev->dev); in fsl_lpspi_probe()
857 return -ENODEV; in fsl_lpspi_probe()
859 is_target = of_property_read_bool((&pdev->dev)->of_node, "spi-slave"); in fsl_lpspi_probe()
861 controller = devm_spi_alloc_target(&pdev->dev, in fsl_lpspi_probe()
864 controller = devm_spi_alloc_host(&pdev->dev, in fsl_lpspi_probe()
868 return -ENOMEM; in fsl_lpspi_probe()
873 fsl_lpspi->dev = &pdev->dev; in fsl_lpspi_probe()
874 fsl_lpspi->is_target = is_target; in fsl_lpspi_probe()
875 fsl_lpspi->is_only_cs1 = of_property_read_bool((&pdev->dev)->of_node, in fsl_lpspi_probe()
876 "fsl,spi-only-use-cs1-sel"); in fsl_lpspi_probe()
877 fsl_lpspi->devtype_data = devtype_data; in fsl_lpspi_probe()
879 init_completion(&fsl_lpspi->xfer_done); in fsl_lpspi_probe()
881 fsl_lpspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in fsl_lpspi_probe()
882 if (IS_ERR(fsl_lpspi->base)) { in fsl_lpspi_probe()
883 ret = PTR_ERR(fsl_lpspi->base); in fsl_lpspi_probe()
886 fsl_lpspi->base_phys = res->start; in fsl_lpspi_probe()
894 ret = devm_request_irq(&pdev->dev, irq, fsl_lpspi_isr, 0, in fsl_lpspi_probe()
895 dev_name(&pdev->dev), fsl_lpspi); in fsl_lpspi_probe()
897 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret); in fsl_lpspi_probe()
901 fsl_lpspi->clk_per = devm_clk_get(&pdev->dev, "per"); in fsl_lpspi_probe()
902 if (IS_ERR(fsl_lpspi->clk_per)) { in fsl_lpspi_probe()
903 ret = PTR_ERR(fsl_lpspi->clk_per); in fsl_lpspi_probe()
907 fsl_lpspi->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in fsl_lpspi_probe()
908 if (IS_ERR(fsl_lpspi->clk_ipg)) { in fsl_lpspi_probe()
909 ret = PTR_ERR(fsl_lpspi->clk_ipg); in fsl_lpspi_probe()
918 ret = pm_runtime_get_sync(fsl_lpspi->dev); in fsl_lpspi_probe()
920 dev_err(fsl_lpspi->dev, "failed to enable clock\n"); in fsl_lpspi_probe()
924 temp = readl(fsl_lpspi->base + IMX7ULP_PARAM); in fsl_lpspi_probe()
925 fsl_lpspi->txfifosize = 1 << (temp & 0x0f); in fsl_lpspi_probe()
926 fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f); in fsl_lpspi_probe()
927 if (of_property_read_u32((&pdev->dev)->of_node, "num-cs", in fsl_lpspi_probe()
929 if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx93-spi")) in fsl_lpspi_probe()
935 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32); in fsl_lpspi_probe()
936 controller->transfer_one = fsl_lpspi_transfer_one; in fsl_lpspi_probe()
937 controller->prepare_transfer_hardware = lpspi_prepare_xfer_hardware; in fsl_lpspi_probe()
938 controller->unprepare_transfer_hardware = lpspi_unprepare_xfer_hardware; in fsl_lpspi_probe()
939 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; in fsl_lpspi_probe()
940 controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX; in fsl_lpspi_probe()
941 controller->dev.of_node = pdev->dev.of_node; in fsl_lpspi_probe()
942 controller->bus_num = pdev->id; in fsl_lpspi_probe()
943 controller->num_chipselect = num_cs; in fsl_lpspi_probe()
944 controller->target_abort = fsl_lpspi_target_abort; in fsl_lpspi_probe()
945 if (!fsl_lpspi->is_target) in fsl_lpspi_probe()
946 controller->use_gpio_descriptors = true; in fsl_lpspi_probe()
948 ret = fsl_lpspi_dma_init(&pdev->dev, fsl_lpspi, controller); in fsl_lpspi_probe()
949 if (ret == -EPROBE_DEFER) in fsl_lpspi_probe()
952 dev_warn(&pdev->dev, "dma setup error %d, use pio\n", ret); in fsl_lpspi_probe()
960 ret = devm_spi_register_controller(&pdev->dev, controller); in fsl_lpspi_probe()
962 dev_err_probe(&pdev->dev, ret, "spi_register_controller error\n"); in fsl_lpspi_probe()
966 pm_runtime_mark_last_busy(fsl_lpspi->dev); in fsl_lpspi_probe()
967 pm_runtime_put_autosuspend(fsl_lpspi->dev); in fsl_lpspi_probe()
974 pm_runtime_dont_use_autosuspend(fsl_lpspi->dev); in fsl_lpspi_probe()
975 pm_runtime_put_sync(fsl_lpspi->dev); in fsl_lpspi_probe()
976 pm_runtime_disable(fsl_lpspi->dev); in fsl_lpspi_probe()
989 pm_runtime_dont_use_autosuspend(fsl_lpspi->dev); in fsl_lpspi_remove()
990 pm_runtime_disable(fsl_lpspi->dev); in fsl_lpspi_remove()