Lines Matching +full:rx +full:- +full:watermark
1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
10 #include <linux/dma-mapping.h>
17 #include <linux/soc/qcom/geni-se.h>
31 * GENI based QUP is a highly-flexible and programmable module for supporting
41 * +-----------------------------------------+
43 * | +----------------------------+ |
44 * --QUP & SE Clocks--> | Serial Engine N | +-IO------>
46 * <---Clock Perf.----+ +----+-----------------------+ | |
50 * <--------AHB-------> | | | |
51 * | | +----+ |
54 * <------SE IRQ------+ +----------------------------+ |
56 * +-----------------------------------------+
61 * used to drive TX & RX operations. On serial interfaces that operate using
62 * master-slave model, primary sequencer drives both TX & RX operations. On
63 * serial interfaces that operate using peer-to-peer model, primary sequencer
64 * drives TX operation and secondary sequencer drives RX operation.
87 * struct geni_wrapper - Data structure to represent the QUP Wrapper Core
101 * struct geni_se_desc - Data structure to represent the QUP Wrapper resources
110 static const char * const icc_path_names[] = {"qup-core", "qup-config",
111 "qup-memory"};
190 * geni_se_get_qup_hw_version() - Read the QUP wrapper Hardware version
197 struct geni_wrapper *wrapper = se->wrapper; in geni_se_get_qup_hw_version()
199 return readl_relaxed(wrapper->base + QUP_HW_VER_REG); in geni_se_get_qup_hw_version()
238 writel_relaxed(0, se->base + SE_GSI_EVENT_EN); in geni_se_irq_clear()
239 writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR); in geni_se_irq_clear()
240 writel_relaxed(0xffffffff, se->base + SE_GENI_S_IRQ_CLEAR); in geni_se_irq_clear()
241 writel_relaxed(0xffffffff, se->base + SE_DMA_TX_IRQ_CLR); in geni_se_irq_clear()
242 writel_relaxed(0xffffffff, se->base + SE_DMA_RX_IRQ_CLR); in geni_se_irq_clear()
243 writel_relaxed(0xffffffff, se->base + SE_IRQ_EN); in geni_se_irq_clear()
247 * geni_se_init() - Initialize the GENI serial engine
249 * @rx_wm: Receive watermark, in units of FIFO words.
250 * @rx_rfr: Ready-for-receive watermark, in units of FIFO words.
253 * receive watermark and ready-for-receive watermarks.
260 geni_se_io_init(se->base); in geni_se_init()
261 geni_se_io_set_mode(se->base); in geni_se_init()
263 writel_relaxed(rx_wm, se->base + SE_GENI_RX_WATERMARK_REG); in geni_se_init()
264 writel_relaxed(rx_rfr, se->base + SE_GENI_RX_RFR_WATERMARK_REG); in geni_se_init()
266 val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); in geni_se_init()
268 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); in geni_se_init()
270 val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); in geni_se_init()
272 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); in geni_se_init()
285 /* Non-UART use only primary sequencer so dont bother about S_IRQ */ in geni_se_select_fifo_mode()
286 val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); in geni_se_select_fifo_mode()
290 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); in geni_se_select_fifo_mode()
293 val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); in geni_se_select_fifo_mode()
296 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN); in geni_se_select_fifo_mode()
308 /* Non-UART use only primary sequencer so dont bother about S_IRQ */ in geni_se_select_dma_mode()
309 val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); in geni_se_select_dma_mode()
313 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); in geni_se_select_dma_mode()
316 val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); in geni_se_select_dma_mode()
319 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN); in geni_se_select_dma_mode()
328 writel(0, se->base + SE_IRQ_EN); in geni_se_select_gpi_mode()
330 val = readl(se->base + SE_GENI_M_IRQ_EN); in geni_se_select_gpi_mode()
333 writel(val, se->base + SE_GENI_M_IRQ_EN); in geni_se_select_gpi_mode()
335 writel(GENI_DMA_MODE_EN, se->base + SE_GENI_DMA_MODE_EN); in geni_se_select_gpi_mode()
337 val = readl(se->base + SE_GSI_EVENT_EN); in geni_se_select_gpi_mode()
339 writel(val, se->base + SE_GSI_EVENT_EN); in geni_se_select_gpi_mode()
343 * geni_se_select_mode() - Select the serial engine transfer mode
371 * GENI FIFO packing is highly configurable. TX/RX packing/unpacking consist
374 * TX FIFO and in GENI_RX_PACKING_CFG0 and GENI_RX_PACKING_CFG1 for RX FIFO.
375 * Refer to below examples for detailed bit-field description.
379 * +-----------+-------+-------+-------+-------+
381 * +-----------+-------+-------+-------+-------+
386 * +-----------+-------+-------+-------+-------+
390 * +-----------+-------+-------+-------+-------+
392 * +-----------+-------+-------+-------+-------+
397 * +-----------+-------+-------+-------+-------+
401 * +-----------+-------+-------+-------+-------+
403 * +-----------+-------+-------+-------+-------+
408 * +-----------+-------+-------+-------+-------+
419 * geni_se_config_packing() - Packing configuration of the serial engine
423 * @msb_to_lsb: Transfer from MSB to LSB or vice-versa.
425 * @rx_cfg: Flag to configure the RX Packing.
436 int idx_start = msb_to_lsb ? bpw - 1 : 0; in geni_se_config_packing()
438 int idx_delta = msb_to_lsb ? -BITS_PER_BYTE : BITS_PER_BYTE; in geni_se_config_packing()
447 len = min_t(int, temp_bpw, BITS_PER_BYTE) - 1; in geni_se_config_packing()
457 temp_bpw = temp_bpw - BITS_PER_BYTE; in geni_se_config_packing()
460 cfg[iter - 1] |= PACKING_STOP_BIT; in geni_se_config_packing()
465 writel_relaxed(cfg0, se->base + SE_GENI_TX_PACKING_CFG0); in geni_se_config_packing()
466 writel_relaxed(cfg1, se->base + SE_GENI_TX_PACKING_CFG1); in geni_se_config_packing()
469 writel_relaxed(cfg0, se->base + SE_GENI_RX_PACKING_CFG0); in geni_se_config_packing()
470 writel_relaxed(cfg1, se->base + SE_GENI_RX_PACKING_CFG1); in geni_se_config_packing()
475 * 0 - 4x8, four words in each entry, max word size of 8 bits in geni_se_config_packing()
476 * 1 - 2x16, two words in each entry, max word size of 16 bits in geni_se_config_packing()
477 * 2 - 1x32, one word in each entry, max word size of 32 bits in geni_se_config_packing()
478 * 3 - undefined in geni_se_config_packing()
481 writel_relaxed(bpw / 16, se->base + SE_GENI_BYTE_GRAN); in geni_se_config_packing()
487 struct geni_wrapper *wrapper = se->wrapper; in geni_se_clks_off()
489 clk_disable_unprepare(se->clk); in geni_se_clks_off()
490 clk_bulk_disable_unprepare(wrapper->num_clks, wrapper->clks); in geni_se_clks_off()
494 * geni_se_resources_off() - Turn off resources associated with the serial
504 if (has_acpi_companion(se->dev)) in geni_se_resources_off()
507 ret = pinctrl_pm_select_sleep_state(se->dev); in geni_se_resources_off()
519 struct geni_wrapper *wrapper = se->wrapper; in geni_se_clks_on()
521 ret = clk_bulk_prepare_enable(wrapper->num_clks, wrapper->clks); in geni_se_clks_on()
525 ret = clk_prepare_enable(se->clk); in geni_se_clks_on()
527 clk_bulk_disable_unprepare(wrapper->num_clks, wrapper->clks); in geni_se_clks_on()
532 * geni_se_resources_on() - Turn on resources associated with the serial
542 if (has_acpi_companion(se->dev)) in geni_se_resources_on()
549 ret = pinctrl_pm_select_default_state(se->dev); in geni_se_resources_on()
558 * geni_se_clk_tbl_get() - Get the clock table to program DFS
575 if (se->clk_perf_tbl) { in geni_se_clk_tbl_get()
576 *tbl = se->clk_perf_tbl; in geni_se_clk_tbl_get()
577 return se->num_clk_levels; in geni_se_clk_tbl_get()
580 se->clk_perf_tbl = devm_kcalloc(se->dev, MAX_CLK_PERF_LEVEL, in geni_se_clk_tbl_get()
581 sizeof(*se->clk_perf_tbl), in geni_se_clk_tbl_get()
583 if (!se->clk_perf_tbl) in geni_se_clk_tbl_get()
584 return -ENOMEM; in geni_se_clk_tbl_get()
587 freq = clk_round_rate(se->clk, freq + 1); in geni_se_clk_tbl_get()
588 if (freq <= 0 || freq == se->clk_perf_tbl[i - 1]) in geni_se_clk_tbl_get()
590 se->clk_perf_tbl[i] = freq; in geni_se_clk_tbl_get()
592 se->num_clk_levels = i; in geni_se_clk_tbl_get()
593 *tbl = se->clk_perf_tbl; in geni_se_clk_tbl_get()
594 return se->num_clk_levels; in geni_se_clk_tbl_get()
599 * geni_se_clk_freq_match() - Get the matching or closest SE clock frequency
612 * - if @exact is true then @res_freq / <an_integer> == @req_freq
613 * - if @exact is false then @res_freq / <an_integer> <= @req_freq
633 return -EINVAL; in geni_se_clk_freq_match()
638 new_delta = req_freq - tbl[i] / divider; in geni_se_clk_freq_match()
654 return -EINVAL; in geni_se_clk_freq_match()
666 * geni_se_tx_init_dma() - Initiate TX DMA transfer on the serial engine
680 writel_relaxed(val, se->base + SE_DMA_TX_IRQ_EN_SET); in geni_se_tx_init_dma()
681 writel_relaxed(lower_32_bits(iova), se->base + SE_DMA_TX_PTR_L); in geni_se_tx_init_dma()
682 writel_relaxed(upper_32_bits(iova), se->base + SE_DMA_TX_PTR_H); in geni_se_tx_init_dma()
683 writel_relaxed(GENI_SE_DMA_EOT_BUF, se->base + SE_DMA_TX_ATTR); in geni_se_tx_init_dma()
684 writel(len, se->base + SE_DMA_TX_LEN); in geni_se_tx_init_dma()
689 * geni_se_tx_dma_prep() - Prepare the serial engine for TX DMA transfer
702 struct geni_wrapper *wrapper = se->wrapper; in geni_se_tx_dma_prep()
705 return -EINVAL; in geni_se_tx_dma_prep()
707 *iova = dma_map_single(wrapper->dev, buf, len, DMA_TO_DEVICE); in geni_se_tx_dma_prep()
708 if (dma_mapping_error(wrapper->dev, *iova)) in geni_se_tx_dma_prep()
709 return -EIO; in geni_se_tx_dma_prep()
717 * geni_se_rx_init_dma() - Initiate RX DMA transfer on the serial engine
720 * @len: Length of the RX buffer.
722 * This function is used to initiate DMA RX transfer.
731 writel_relaxed(val, se->base + SE_DMA_RX_IRQ_EN_SET); in geni_se_rx_init_dma()
732 writel_relaxed(lower_32_bits(iova), se->base + SE_DMA_RX_PTR_L); in geni_se_rx_init_dma()
733 writel_relaxed(upper_32_bits(iova), se->base + SE_DMA_RX_PTR_H); in geni_se_rx_init_dma()
734 /* RX does not have EOT buffer type bit. So just reset RX_ATTR */ in geni_se_rx_init_dma()
735 writel_relaxed(0, se->base + SE_DMA_RX_ATTR); in geni_se_rx_init_dma()
736 writel(len, se->base + SE_DMA_RX_LEN); in geni_se_rx_init_dma()
741 * geni_se_rx_dma_prep() - Prepare the serial engine for RX DMA transfer
743 * @buf: Pointer to the RX buffer.
744 * @len: Length of the RX buffer.
747 * This function is used to prepare the buffers for DMA RX.
754 struct geni_wrapper *wrapper = se->wrapper; in geni_se_rx_dma_prep()
757 return -EINVAL; in geni_se_rx_dma_prep()
759 *iova = dma_map_single(wrapper->dev, buf, len, DMA_FROM_DEVICE); in geni_se_rx_dma_prep()
760 if (dma_mapping_error(wrapper->dev, *iova)) in geni_se_rx_dma_prep()
761 return -EIO; in geni_se_rx_dma_prep()
769 * geni_se_tx_dma_unprep() - Unprepare the serial engine after TX DMA transfer
778 struct geni_wrapper *wrapper = se->wrapper; in geni_se_tx_dma_unprep()
780 if (!dma_mapping_error(wrapper->dev, iova)) in geni_se_tx_dma_unprep()
781 dma_unmap_single(wrapper->dev, iova, len, DMA_TO_DEVICE); in geni_se_tx_dma_unprep()
786 * geni_se_rx_dma_unprep() - Unprepare the serial engine after RX DMA transfer
788 * @iova: DMA address of the RX buffer.
789 * @len: Length of the RX buffer.
791 * This function is used to unprepare the DMA buffers after DMA RX.
795 struct geni_wrapper *wrapper = se->wrapper; in geni_se_rx_dma_unprep()
797 if (!dma_mapping_error(wrapper->dev, iova)) in geni_se_rx_dma_unprep()
798 dma_unmap_single(wrapper->dev, iova, len, DMA_FROM_DEVICE); in geni_se_rx_dma_unprep()
805 const char *icc_names[] = {"qup-core", "qup-config", icc_ddr}; in geni_icc_get()
807 if (has_acpi_companion(se->dev)) in geni_icc_get()
810 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { in geni_icc_get()
814 se->icc_paths[i].path = devm_of_icc_get(se->dev, icc_names[i]); in geni_icc_get()
815 if (IS_ERR(se->icc_paths[i].path)) in geni_icc_get()
822 err = PTR_ERR(se->icc_paths[i].path); in geni_icc_get()
823 if (err != -EPROBE_DEFER) in geni_icc_get()
824 dev_err_ratelimited(se->dev, "Failed to get ICC path '%s': %d\n", in geni_icc_get()
835 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { in geni_icc_set_bw()
836 ret = icc_set_bw(se->icc_paths[i].path, in geni_icc_set_bw()
837 se->icc_paths[i].avg_bw, se->icc_paths[i].avg_bw); in geni_icc_set_bw()
839 dev_err_ratelimited(se->dev, "ICC BW voting failed on path '%s': %d\n", in geni_icc_set_bw()
853 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) in geni_icc_set_tag()
854 icc_set_tag(se->icc_paths[i].path, tag); in geni_icc_set_tag()
863 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { in geni_icc_enable()
864 ret = icc_enable(se->icc_paths[i].path); in geni_icc_enable()
866 dev_err_ratelimited(se->dev, "ICC enable failed on path '%s': %d\n", in geni_icc_enable()
880 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { in geni_icc_disable()
881 ret = icc_disable(se->icc_paths[i].path); in geni_icc_disable()
883 dev_err_ratelimited(se->dev, "ICC disable failed on path '%s': %d\n", in geni_icc_disable()
895 struct device *dev = &pdev->dev; in geni_se_probe()
901 return -ENOMEM; in geni_se_probe()
903 wrapper->dev = dev; in geni_se_probe()
904 wrapper->base = devm_platform_ioremap_resource(pdev, 0); in geni_se_probe()
905 if (IS_ERR(wrapper->base)) in geni_se_probe()
906 return PTR_ERR(wrapper->base); in geni_se_probe()
908 if (!has_acpi_companion(&pdev->dev)) { in geni_se_probe()
912 desc = device_get_match_data(&pdev->dev); in geni_se_probe()
914 return -EINVAL; in geni_se_probe()
916 wrapper->num_clks = min_t(unsigned int, desc->num_clks, MAX_CLKS); in geni_se_probe()
918 for (i = 0; i < wrapper->num_clks; ++i) in geni_se_probe()
919 wrapper->clks[i].id = desc->clks[i]; in geni_se_probe()
921 ret = of_count_phandle_with_args(dev->of_node, "clocks", "#clock-cells"); in geni_se_probe()
923 dev_err(dev, "invalid clocks property at %pOF\n", dev->of_node); in geni_se_probe()
927 if (ret < wrapper->num_clks) { in geni_se_probe()
929 dev->of_node, wrapper->num_clks); in geni_se_probe()
930 return -EINVAL; in geni_se_probe()
933 ret = devm_clk_bulk_get(dev, wrapper->num_clks, wrapper->clks); in geni_se_probe()
946 "m-ahb",
947 "s-ahb",
956 "s-ahb",
965 { .compatible = "qcom,geni-se-qup", .data = &qup_desc },
966 { .compatible = "qcom,geni-se-i2c-master-hub", .data = &i2c_master_hub_desc },