Lines Matching +full:rx +full:- +full:watermark
1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2018-2019 SiFive
8 * - drivers/tty/serial/pxa.c
9 * - drivers/tty/serial/amba-pl011.c
10 * - drivers/tty/serial/uartlite.c
11 * - drivers/tty/serial/omap-serial.c
12 * - drivers/pwm/pwm-sifive.c
15 * - Chapter 19 "Universal Asynchronous Receiver/Transmitter (UART)" of
16 * SiFive FE310-G000 v2p3
17 * - The tree/master/src/main/scala/devices/uart directory of
18 * https://github.com/sifive/sifive-blocks/
20 * The SiFive UART design is not 8250-compatible. The following common
22 * - Word lengths other than 8 bits
23 * - Break handling
24 * - Parity
25 * - Flow control
26 * - Modem signals (DSR, RI, etc.)
117 #define SIFIVE_SERIAL_NAME "sifive-serial"
129 #error Driver does not support configurations with different TX, RX FIFO sizes
137 * struct sifive_serial_port - driver-specific data extension to struct uart_port
157 * Structure container-of macros
178 * __ssp_early_writel() - write to a SiFive serial port register (early)
191 writel_relaxed(v, port->membase + offs); in __ssp_early_writel()
195 * __ssp_early_readl() - read from a SiFive serial port register (early)
211 return readl_relaxed(port->membase + offs); in __ssp_early_readl()
215 * __ssp_writel() - write to a SiFive serial port register
227 __ssp_early_writel(v, offs, &ssp->port); in __ssp_writel()
231 * __ssp_readl() - read from a SiFive serial port register
244 return __ssp_early_readl(&ssp->port, offs); in __ssp_readl()
248 * sifive_serial_is_txfifo_full() - is the TXFIFO full?
251 * Read the transmit FIFO "full" bit, returning a non-zero value if the
255 * Returns: SIFIVE_SERIAL_TXDATA_FULL_MASK (non-zero) if the transmit FIFO
265 * __ssp_transmit_char() - enqueue a byte to transmit onto the TX FIFO
281 * __ssp_transmit_chars() - enqueue multiple bytes onto the TX FIFO
287 * Context: Any context. Expects @ssp->port.lock to be held by caller.
293 uart_port_tx_limited(&ssp->port, ch, SIFIVE_TX_FIFO_DEPTH, in __ssp_transmit_chars()
300 * __ssp_enable_txwm() - enable transmit watermark interrupts
303 * Enable interrupt generation when the transmit FIFO watermark is reached
308 if (ssp->ier & SIFIVE_SERIAL_IE_TXWM_MASK) in __ssp_enable_txwm()
311 ssp->ier |= SIFIVE_SERIAL_IE_TXWM_MASK; in __ssp_enable_txwm()
312 __ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp); in __ssp_enable_txwm()
316 * __ssp_enable_rxwm() - enable receive watermark interrupts
319 * Enable interrupt generation when the receive FIFO watermark is reached
324 if (ssp->ier & SIFIVE_SERIAL_IE_RXWM_MASK) in __ssp_enable_rxwm()
327 ssp->ier |= SIFIVE_SERIAL_IE_RXWM_MASK; in __ssp_enable_rxwm()
328 __ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp); in __ssp_enable_rxwm()
332 * __ssp_disable_txwm() - disable transmit watermark interrupts
335 * Disable interrupt generation when the transmit FIFO watermark is reached
340 if (!(ssp->ier & SIFIVE_SERIAL_IE_TXWM_MASK)) in __ssp_disable_txwm()
343 ssp->ier &= ~SIFIVE_SERIAL_IE_TXWM_MASK; in __ssp_disable_txwm()
344 __ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp); in __ssp_disable_txwm()
348 * __ssp_disable_rxwm() - disable receive watermark interrupts
351 * Disable interrupt generation when the receive FIFO watermark is reached
356 if (!(ssp->ier & SIFIVE_SERIAL_IE_RXWM_MASK)) in __ssp_disable_rxwm()
359 ssp->ier &= ~SIFIVE_SERIAL_IE_RXWM_MASK; in __ssp_disable_rxwm()
360 __ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp); in __ssp_disable_rxwm()
364 * __ssp_receive_char() - receive a byte from the UART
366 * @is_empty: char pointer to return whether the RX FIFO is empty
368 * Try to read a byte from the SiFive UART RX FIFO, referenced by
369 * @ssp, and to return it. Also returns the RX FIFO empty bit in
373 * Returns: the byte read from the UART RX FIFO.
395 * __ssp_receive_chars() - receive multiple bytes from the UART
398 * Receive up to an RX FIFO's worth of bytes from the SiFive UART referred
401 * Context: Expects ssp->port.lock to be held by caller.
409 for (c = SIFIVE_RX_FIFO_DEPTH; c > 0; --c) { in __ssp_receive_chars()
414 ssp->port.icount.rx++; in __ssp_receive_chars()
415 if (!uart_prepare_sysrq_char(&ssp->port, ch)) in __ssp_receive_chars()
416 uart_insert_char(&ssp->port, 0, 0, ch, TTY_NORMAL); in __ssp_receive_chars()
419 tty_flip_buffer_push(&ssp->port.state->port); in __ssp_receive_chars()
423 * __ssp_update_div() - calculate the divisor setting by the line rate
434 div = DIV_ROUND_UP(ssp->port.uartclk, ssp->baud_rate) - 1; in __ssp_update_div()
440 * __ssp_update_baud_rate() - set the UART "baud rate"
452 if (ssp->baud_rate == rate) in __ssp_update_baud_rate()
455 ssp->baud_rate = rate; in __ssp_update_baud_rate()
460 * __ssp_set_stop_bits() - set the number of stop bits
477 v |= (nstop - 1) << SIFIVE_SERIAL_TXCTRL_NSTOP_SHIFT; in __ssp_set_stop_bits()
482 * __ssp_wait_for_xmitr() - wait for an empty slot on the TX FIFO
525 uart_port_lock(&ssp->port); in sifive_serial_irq()
529 uart_port_unlock(&ssp->port); in sifive_serial_irq()
538 uart_unlock_and_check_sysrq(&ssp->port); in sifive_serial_irq()
581 * sifive_serial_clk_notifier() - clock post-rate-change notifier
587 * after a synchronous divide-by-two divider, so any CPU clock rate change
601 * The TX watermark is always set to 1 by this driver, which in sifive_serial_clk_notifier()
603 * left in the TX queue -- in other words, when the TX FIFO is in sifive_serial_clk_notifier()
616 udelay(DIV_ROUND_UP(12 * 1000 * 1000, ssp->baud_rate)); in sifive_serial_clk_notifier()
619 if (event == POST_RATE_CHANGE && ssp->port.uartclk != cnd->new_rate) { in sifive_serial_clk_notifier()
620 ssp->port.uartclk = cnd->new_rate; in sifive_serial_clk_notifier()
637 if ((termios->c_cflag & CSIZE) != CS8) { in sifive_serial_set_termios()
638 dev_err_once(ssp->port.dev, "only 8-bit words supported\n"); in sifive_serial_set_termios()
639 termios->c_cflag &= ~CSIZE; in sifive_serial_set_termios()
640 termios->c_cflag |= CS8; in sifive_serial_set_termios()
642 if (termios->c_iflag & (INPCK | PARMRK)) in sifive_serial_set_termios()
643 dev_err_once(ssp->port.dev, "parity checking not supported\n"); in sifive_serial_set_termios()
644 if (termios->c_iflag & BRKINT) in sifive_serial_set_termios()
645 dev_err_once(ssp->port.dev, "BREAK detection not supported\n"); in sifive_serial_set_termios()
646 termios->c_iflag &= ~(INPCK|PARMRK|BRKINT); in sifive_serial_set_termios()
649 nstop = (termios->c_cflag & CSTOPB) ? 2 : 1; in sifive_serial_set_termios()
654 ssp->port.uartclk / 16); in sifive_serial_set_termios()
657 uart_port_lock_irqsave(&ssp->port, &flags); in sifive_serial_set_termios()
659 /* Update the per-port timeout */ in sifive_serial_set_termios()
660 uart_update_timeout(port, termios->c_cflag, rate); in sifive_serial_set_termios()
662 ssp->port.read_status_mask = 0; in sifive_serial_set_termios()
667 if ((termios->c_cflag & CREAD) == 0) in sifive_serial_set_termios()
674 uart_port_unlock_irqrestore(&ssp->port, flags); in sifive_serial_set_termios()
690 ssp->port.type = PORT_SIFIVE_V0; in sifive_serial_config_port()
696 return -EINVAL; in sifive_serial_verify_port()
701 return port->type == PORT_SIFIVE_V0 ? "SiFive UART v0" : NULL; in sifive_serial_type()
744 struct earlycon_device *dev = con->data; in early_sifive_serial_write()
745 struct uart_port *port = &dev->port; in early_sifive_serial_write()
753 struct uart_port *port = &dev->port; in early_sifive_serial_setup()
755 if (!port->membase) in early_sifive_serial_setup()
756 return -ENODEV; in early_sifive_serial_setup()
758 dev->con->write = early_sifive_serial_write; in early_sifive_serial_setup()
764 OF_EARLYCON_DECLARE(sifive, "sifive,fu540-c000-uart",
787 struct sifive_serial_port *ssp = sifive_serial_console_ports[co->index]; in sifive_serial_console_write()
796 locked = uart_port_trylock_irqsave(&ssp->port, &flags); in sifive_serial_console_write()
798 uart_port_lock_irqsave(&ssp->port, &flags); in sifive_serial_console_write()
803 uart_console_write(&ssp->port, s, count, sifive_serial_console_putchar); in sifive_serial_console_write()
808 uart_port_unlock_irqrestore(&ssp->port, flags); in sifive_serial_console_write()
819 if (co->index < 0 || co->index >= SIFIVE_SERIAL_MAX_PORTS) in sifive_serial_console_setup()
820 return -ENODEV; in sifive_serial_console_setup()
822 ssp = sifive_serial_console_ports[co->index]; in sifive_serial_console_setup()
824 return -ENODEV; in sifive_serial_console_setup()
829 return uart_set_options(&ssp->port, co, baud, parity, bits, flow); in sifive_serial_console_setup()
840 .index = -1,
854 sifive_serial_console_ports[ssp->port.line] = ssp; in __ssp_add_console_port()
859 sifive_serial_console_ports[ssp->port.line] = NULL; in __ssp_remove_console_port()
915 return -EPROBE_DEFER; in sifive_serial_probe()
921 clk = devm_clk_get_enabled(&pdev->dev, NULL); in sifive_serial_probe()
923 dev_err(&pdev->dev, "unable to find controller clock\n"); in sifive_serial_probe()
927 id = of_alias_get_id(pdev->dev.of_node, "serial"); in sifive_serial_probe()
929 dev_err(&pdev->dev, "missing aliases entry\n"); in sifive_serial_probe()
935 dev_err(&pdev->dev, "too many UARTs (%d)\n", id); in sifive_serial_probe()
936 return -EINVAL; in sifive_serial_probe()
940 ssp = devm_kzalloc(&pdev->dev, sizeof(*ssp), GFP_KERNEL); in sifive_serial_probe()
942 return -ENOMEM; in sifive_serial_probe()
944 ssp->port.dev = &pdev->dev; in sifive_serial_probe()
945 ssp->port.type = PORT_SIFIVE_V0; in sifive_serial_probe()
946 ssp->port.iotype = UPIO_MEM; in sifive_serial_probe()
947 ssp->port.irq = irq; in sifive_serial_probe()
948 ssp->port.fifosize = SIFIVE_TX_FIFO_DEPTH; in sifive_serial_probe()
949 ssp->port.ops = &sifive_serial_uops; in sifive_serial_probe()
950 ssp->port.line = id; in sifive_serial_probe()
951 ssp->port.mapbase = mem->start; in sifive_serial_probe()
952 ssp->port.membase = base; in sifive_serial_probe()
953 ssp->dev = &pdev->dev; in sifive_serial_probe()
954 ssp->clk = clk; in sifive_serial_probe()
955 ssp->clk_notifier.notifier_call = sifive_serial_clk_notifier; in sifive_serial_probe()
957 r = clk_notifier_register(ssp->clk, &ssp->clk_notifier); in sifive_serial_probe()
959 dev_err(&pdev->dev, "could not register clock notifier: %d\n", in sifive_serial_probe()
965 ssp->port.uartclk = clk_get_rate(ssp->clk); in sifive_serial_probe()
966 ssp->baud_rate = SIFIVE_DEFAULT_BAUD_RATE; in sifive_serial_probe()
971 /* Enable transmits and set the watermark level to 1 */ in sifive_serial_probe()
976 /* Enable receives and set the watermark level to 0 */ in sifive_serial_probe()
981 r = request_irq(ssp->port.irq, sifive_serial_irq, ssp->port.irqflags, in sifive_serial_probe()
982 dev_name(&pdev->dev), ssp); in sifive_serial_probe()
984 dev_err(&pdev->dev, "could not attach interrupt: %d\n", r); in sifive_serial_probe()
990 r = uart_add_one_port(&sifive_serial_uart_driver, &ssp->port); in sifive_serial_probe()
992 dev_err(&pdev->dev, "could not add uart: %d\n", r); in sifive_serial_probe()
1000 free_irq(ssp->port.irq, ssp); in sifive_serial_probe()
1002 clk_notifier_unregister(ssp->clk, &ssp->clk_notifier); in sifive_serial_probe()
1012 uart_remove_one_port(&sifive_serial_uart_driver, &ssp->port); in sifive_serial_remove()
1013 free_irq(ssp->port.irq, ssp); in sifive_serial_remove()
1014 clk_notifier_unregister(ssp->clk, &ssp->clk_notifier); in sifive_serial_remove()
1021 return uart_suspend_port(&sifive_serial_uart_driver, &ssp->port); in sifive_serial_suspend()
1028 return uart_resume_port(&sifive_serial_uart_driver, &ssp->port); in sifive_serial_resume()
1035 { .compatible = "sifive,fu540-c000-uart" },