atheros/atlx/atl2.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* atl2.h -- atl2 driver definitions
9  * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
39 	((a)->hw_addr + (reg))))
41 #define ATL2_WRITE_FLUSH(a) (ioread32((a)->hw_addr))
43 #define ATL2_READ_REG(a, reg) (ioread32((a)->hw_addr + (reg)))
46 	((a)->hw_addr + (reg))))
48 #define ATL2_READ_REGB(a, reg) (ioread8((a)->hw_addr + (reg)))
51 	((a)->hw_addr + (reg))))
53 #define ATL2_READ_REGW(a, reg) (ioread16((a)->hw_addr + (reg)))
56 	(iowrite32((value), (((a)->hw_addr + (reg)) + ((offset) << 2))))
59 	(ioread32(((a)->hw_addr + (reg)) + ((offset) << 2)))
88 #define IDLE_STATUS_RXMAC	1	/* 1: RXMAC is non-IDLE */
89 #define IDLE_STATUS_TXMAC	2	/* 1: TXMAC is non-IDLE */
90 #define IDLE_STATUS_DMAR	8	/* 1: DMAR is non-IDLE */
91 #define IDLE_STATUS_DMAW	4	/* 1: DMAW is non-IDLE */
110 					 * Data Mem low 32-bit(dword align) */
114 					 * Status Memory low 32-bit(dword word
119 					 * Status Memory low 32-bit(unit 8
129 /* TX Cur-Through (early tx threshold) Control Register */
138 #define REG_PAUSE_ON_TH		0x15A8	/* RXD high watermark of overflow
140 #define REG_PAUSE_OFF_TH	0x15AA	/* RXD lower watermark of overflow
161 #define ISR_HOST_RXD_OV	0x100	/* Host rx data memory full , one pulse */
168 #define ISR_RS_UPDATE	0x20000	/* interrupt ater new rx pkt status written
190 #define REG_STS_RXD_OV		0x1704	/* Num frames dropped due to RX
192 #define REG_STS_RXS_OV		0x1708	/* Num frames dropped due to RX
341 	unsigned char     	packet[1536-sizeof(struct rx_pkt_status)];
353 	/* op-code */
374 				* control in half-duplex mode. In unit of
375 				* 8-bit time. */
376 	u8 ipgt;               /* Desired back to back inter-packet gap. The
377 				* default is 96-bit time. */
379 				* RX frames. Frame gap below such IFP is
381 	u8 ipgr1;              /* 64bit Carrier-Sense window */
382 	u8 ipgr2;              /* 96-bit IPG window */
383 	u8 retry_buf;          /* When half-duplex mode, should hold some