| /linux-6.12.1/drivers/isdn/mISDN/ |
| D | layer2.c | 92 struct layer2 *l2 = fi->userdata; in l2m_debug() local
104 printk(KERN_DEBUG "%s l2 (sapi %d tei %d): %pV\n", in l2m_debug()
105 mISDNDevName4ch(&l2->ch), l2->sapi, l2->tei, &vaf); in l2m_debug()
111 l2headersize(struct layer2 *l2, int ui) in l2headersize() argument
113 return ((test_bit(FLG_MOD128, &l2->flag) && (!ui)) ? 2 : 1) + in l2headersize()
114 (test_bit(FLG_LAPD, &l2->flag) ? 2 : 1); in l2headersize()
118 l2addrsize(struct layer2 *l2) in l2addrsize() argument
120 return test_bit(FLG_LAPD, &l2->flag) ? 2 : 1; in l2addrsize()
124 l2_newid(struct layer2 *l2) in l2_newid() argument
128 id = l2->next_id++; in l2_newid()
[all …]
|
| D | tei.c | 109 struct layer2 *l2; in da_deactivate() local
113 list_for_each_entry(l2, &mgr->layer2, list) { in da_deactivate()
114 if (l2->l2m.state > ST_L2_4) { in da_deactivate()
146 struct layer2 *l2; in da_timer() local
151 list_for_each_entry(l2, &mgr->layer2, list) { in da_timer()
152 if (l2->l2m.state > ST_L2_4) { in da_timer()
234 tm->l2->sapi, tm->l2->tei, &vaf); in tei_debug()
246 struct layer2 *l2; in get_free_id() local
248 list_for_each_entry(l2, &mgr->layer2, list) { in get_free_id()
249 if (l2->ch.nr > 63) { in get_free_id()
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/amdzen5/ |
| D | l2-cache.json | 5 …"BriefDescription": "L2 cache requests of non-cacheable type (non-cached data and instructions rea…
11 …"BriefDescription": "L2 cache requests: from hardware prefetchers to prefetch directly into L2 (hi…
17 "BriefDescription": "L2 cache requests: prefetch directly into L2.",
23 "BriefDescription": "L2 cache requests: instruction cache reads.",
29 "BriefDescription": "L2 cache requests: data cache shared reads.",
35 "BriefDescription": "L2 cache requests: data cache stores.",
41 …"BriefDescription": "L2 cache requests: data cache reads including hardware and software prefetch.…
47 …"BriefDescription": "L2 cache requests of common types from L1 data cache (including prefetches).",
53 "BriefDescription": "L2 cache requests of common types not including prefetches.",
59 "BriefDescription": "L2 cache requests of all types.",
[all …]
|
| /linux-6.12.1/Documentation/devicetree/bindings/cache/ |
| D | freescale-l2cache.txt | 1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
9 "fsl,b4420-l2-cache-controller"
10 "fsl,b4860-l2-cache-controller"
11 "fsl,bsc9131-l2-cache-controller"
12 "fsl,bsc9132-l2-cache-controller"
13 "fsl,c293-l2-cache-controller"
14 "fsl,mpc8536-l2-cache-controller"
15 "fsl,mpc8540-l2-cache-controller"
16 "fsl,mpc8541-l2-cache-controller"
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/amdzen4/ |
| D | cache.json | 23 "BriefDescription": "Demand data cache fills from local L2 cache.",
29 …"BriefDescription": "Demand data cache fills from L3 cache or different L2 cache in the same CCX.",
71 "BriefDescription": "Any data cache fills from local L2 cache.",
77 "BriefDescription": "Any data cache fills from L3 cache or different L2 cache in the same CCX.",
83 …"BriefDescription": "Any data cache fills from local L2 cache or L3 cache or different L2 cache in…
149 …move data to all cache levels except L1) and T2 (move data to all cache levels except L1 and L2).",
191 "BriefDescription": "Software prefetch data cache fills from local L2 cache.",
197 …"BriefDescription": "Software prefetch data cache fills from L3 cache or different L2 cache in the…
239 "BriefDescription": "Hardware prefetch data cache fills from local L2 cache.",
245 …"BriefDescription": "Hardware prefetch data cache fills from L3 cache or different L2 cache in the…
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/amdzen1/ |
| D | cache.json | 15 …"BriefDescription": "The number of 64 byte instruction cache line was fulfilled from the L2 cache."
25 …fDescription": "The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
30 "BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs."
58 …"BriefDescription": "IC line invalidated due to L2 invalidating probe (external or LS). The number…
75 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
81 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
87 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
93 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
99 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
105 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
[all …]
|
| /linux-6.12.1/drivers/memory/ |
| D | bt1-l2-ctl.c | 8 * Baikal-T1 CM2 L2-cache Control Block driver.
38 * struct l2_ctl - Baikal-T1 L2 Control block private data.
49 * enum l2_ctl_stall - Baikal-T1 L2-cache-RAM stall identifier.
61 * struct l2_ctl_device_attribute - Baikal-T1 L2-cache device attribute.
63 * @id: L2-cache stall field identifier.
77 static int l2_ctl_get_latency(struct l2_ctl *l2, enum l2_ctl_stall id, u32 *val) in l2_ctl_get_latency() argument
82 ret = regmap_read(l2->sys_regs, L2_CTL_REG, &data); in l2_ctl_get_latency()
103 static int l2_ctl_set_latency(struct l2_ctl *l2, enum l2_ctl_stall id, u32 val) in l2_ctl_set_latency() argument
130 ret = regmap_update_bits(l2->sys_regs, L2_CTL_REG, mask, data); in l2_ctl_set_latency()
134 return regmap_read_poll_timeout(l2->sys_regs, L2_CTL_REG, data, in l2_ctl_set_latency()
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/amdzen2/ |
| D | cache.json | 5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/amdzen3/ |
| D | cache.json | 5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …fDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Re…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …tion": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/bonnell/ |
| D | cache.json | 59 "BriefDescription": "Cycles L2 address bus is in use.",
107 "BriefDescription": "Cycles the L2 cache data bus is busy.",
115 "BriefDescription": "Cycles the L2 transfers data to the core.",
123 "BriefDescription": "L2 cacheable instruction fetch requests",
131 "BriefDescription": "L2 cacheable instruction fetch requests",
139 "BriefDescription": "L2 cacheable instruction fetch requests",
147 "BriefDescription": "L2 cacheable instruction fetch requests",
155 "BriefDescription": "L2 cacheable instruction fetch requests",
163 "BriefDescription": "L2 cache reads",
171 "BriefDescription": "L2 cache reads",
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/goldmont/ |
| D | cache.json | 33 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the i…
37 "BriefDescription": "L2 cache request misses",
41 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
46 "BriefDescription": "L2 cache requests",
50 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
61 … ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit…
99 "BriefDescription": "Load uops retired that hit L2 (Precise event capable)",
105 "PublicDescription": "Counts load uops retired that hit in the L2 cache.",
110 "BriefDescription": "Load uops retired that missed L2 (Precise event capable)",
116 "PublicDescription": "Counts load uops retired that miss in the L2 cache.",
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/goldmontplus/ |
| D | cache.json | 33 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the i…
37 "BriefDescription": "L2 cache request misses",
41 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
46 "BriefDescription": "L2 cache requests",
50 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
61 … ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit…
99 "BriefDescription": "Load uops retired that hit L2 (Precise event capable)",
105 "PublicDescription": "Counts load uops retired that hit in the L2 cache.",
110 "BriefDescription": "Load uops retired that missed L2 (Precise event capable)",
116 "PublicDescription": "Counts load uops retired that miss in the L2 cache.",
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/haswell/ |
| D | cache.json | 57 "BriefDescription": "Not rejected writebacks that hit L2 cache",
61 "PublicDescription": "Not rejected writebacks that hit L2 cache.",
66 "BriefDescription": "L2 cache lines filling L2",
70 …event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2…
75 "BriefDescription": "L2 cache lines in E state filling L2",
79 "PublicDescription": "L2 cache lines in E state filling L2.",
84 "BriefDescription": "L2 cache lines in I state filling L2",
88 "PublicDescription": "L2 cache lines in I state filling L2.",
93 "BriefDescription": "L2 cache lines in S state filling L2",
97 "PublicDescription": "L2 cache lines in S state filling L2.",
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/broadwellde/ |
| D | cache.json | 50 "BriefDescription": "Not rejected writebacks that hit L2 cache",
54 "PublicDescription": "This event counts the number of WB requests that hit L2 cache.",
59 "BriefDescription": "L2 cache lines filling L2",
63 …"PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does…
68 "BriefDescription": "L2 cache lines in E state filling L2",
72 …licDescription": "This event counts the number of L2 cache lines in the Exclusive state filling th…
77 "BriefDescription": "L2 cache lines in I state filling L2",
81 …licDescription": "This event counts the number of L2 cache lines in the Invalidate state filling t…
86 "BriefDescription": "L2 cache lines in S state filling L2",
90 …ublicDescription": "This event counts the number of L2 cache lines in the Shared state filling the…
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/haswellx/ |
| D | cache.json | 57 "BriefDescription": "Not rejected writebacks that hit L2 cache",
61 "PublicDescription": "Not rejected writebacks that hit L2 cache.",
66 "BriefDescription": "L2 cache lines filling L2",
70 …event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2…
75 "BriefDescription": "L2 cache lines in E state filling L2",
79 "PublicDescription": "L2 cache lines in E state filling L2.",
84 "BriefDescription": "L2 cache lines in I state filling L2",
88 "PublicDescription": "L2 cache lines in I state filling L2.",
93 "BriefDescription": "L2 cache lines in S state filling L2",
97 "PublicDescription": "L2 cache lines in S state filling L2.",
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/ivybridge/ |
| D | cache.json | 51 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
59 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",
63 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.",
68 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state",
72 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.",
77 …"BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-reject…
86 "BriefDescription": "L2 cache lines filling L2",
90 "PublicDescription": "L2 cache lines filling L2.",
95 "BriefDescription": "L2 cache lines in E state filling L2",
99 "PublicDescription": "L2 cache lines in E state filling L2.",
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/knightslanding/ |
| D | cache.json | 3 … number of MEC requests that were not accepted into the L2Q because of any L2 queue reject condit…
26 "BriefDescription": "Counts the number of L2 cache misses",
34 "BriefDescription": "Counts the total number of L2 cache references.",
42 … a cache line (cacheable requests) excluding SW prefetches filling only to L2 cache and L1 evictio…
87 …"BriefDescription": "Counts the number of load micro-ops retired that hit in the L2 (Precise Event…
93 …ion": "This event counts the number of load micro-uops retired that hit in the L2 (Precise Event)",
98 …"BriefDescription": "Counts the number of load micro-ops retired that miss in the L2 (Precise Even…
104 …ion": "This event counts the number of load micro-ops retired that miss in the L2 (Precise Event)",
135 … forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Vali…
145 …rwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid …
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/broadwellx/ |
| D | cache.json | 50 "BriefDescription": "Not rejected writebacks that hit L2 cache",
54 "PublicDescription": "This event counts the number of WB requests that hit L2 cache.",
59 "BriefDescription": "L2 cache lines filling L2",
63 …"PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does…
68 "BriefDescription": "L2 cache lines in E state filling L2",
72 …licDescription": "This event counts the number of L2 cache lines in the Exclusive state filling th…
77 "BriefDescription": "L2 cache lines in I state filling L2",
81 …licDescription": "This event counts the number of L2 cache lines in the Invalidate state filling t…
86 "BriefDescription": "L2 cache lines in S state filling L2",
90 …ublicDescription": "This event counts the number of L2 cache lines in the Shared state filling the…
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/ivytown/ |
| D | cache.json | 51 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
59 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",
63 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.",
68 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state",
72 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.",
77 …"BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-reject…
86 "BriefDescription": "L2 cache lines filling L2",
90 "PublicDescription": "L2 cache lines filling L2.",
95 "BriefDescription": "L2 cache lines in E state filling L2",
99 "PublicDescription": "L2 cache lines in E state filling L2.",
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/graniterapids/ |
| D | cache.json | 40 …scription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
44 …nts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand re…
68 "BriefDescription": "L2 cache lines filling L2",
72 …"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover …
77 …riefDescription": "Modified cache lines that are evicted by L2 cache when triggered by an L2 cache…
81 …scription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache…
86 …on": "Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache…
90 …": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache…
95 …"BriefDescription": "Cache lines that have been L2 hardware prefetched but not used by demand acce…
99 …ines that have been prefetched by the L2 hardware prefetcher but not used by demand access when ev…
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/silvermont/ |
| D | cache.json | 7 … eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests …
20 … "BriefDescription": "Counts the number of request from the L2 that were not accepted into the XQ",
24 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the I…
28 "BriefDescription": "L2 cache request misses",
32 …licDescription": "This event counts the total number of L2 cache references and the number of L2 c…
37 "BriefDescription": "L2 cache requests from this core",
41 …his event counts requests originating from the core that references a cache line in the L2 cache.",
83 "BriefDescription": "Loads hit L2",
88 "PublicDescription": "This event counts the number of load ops retired that hit in the L2.",
93 "BriefDescription": "Loads missed L2",
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/powerpc/power10/ |
| D | datasource.json | 15 …ocessor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss…
40 … "All successful D-Side Load dispatches for this thread that missed in the L2. Since the event hap…
45 …"All successful D-Side Store dispatches for this thread that missed in the L2. Since the event hap…
50 …"BriefDescription": "All successful D-side store dispatches for this thread that were L2 hits. Sin…
55 …uction (demand and prefetch) dispatches for this thread that missed in the L2. Since the event hap…
60 …"BriefDescription": "The processor's instruction cache was reloaded from the local core's L2 due t…
65 …"BriefDescription": "The processor's L1 data cache was reloaded from the local core's L2 due to a …
70 …"BriefDescription": "The processor's instruction cache was reloaded from the local core's L2 due t…
75 …"BriefDescription": "The processor's L1 data cache was reloaded from the local core's L2 due to a …
100 …t dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss…
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/ |
| D | cache.json | 102 …L2 cache refill due to prefetch. If the complex is configured with a per-complex L2 cache, this ev…
105 …L2 cache refill due to prefetch. If the complex is configured with a per-complex L2 cache, this ev…
114 …: "L2 cache write streaming mode. This event counts for each cycle where the core is in write stre…
117 …: "L2 cache write streaming mode. This event counts for each cycle where the core is in write stre…
144 … "PublicDescription": "L2 TLB walk cache access. This event does not count if the MMU is disabled",
147 … "BriefDescription": "L2 TLB walk cache access. This event does not count if the MMU is disabled"
150 … "PublicDescription": "L2 TLB walk cache refill. This event does not count if the MMU is disabled",
153 … "BriefDescription": "L2 TLB walk cache refill. This event does not count if the MMU is disabled"
156 …"PublicDescription": "L2 TLB IPA cache access. This event counts on each access to the IPA cache. …
159 …"BriefDescription": "L2 TLB IPA cache access. This event counts on each access to the IPA cache. I…
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/tigerlake/ |
| D | cache.json | 32 …scription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
36 …nts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand re…
60 "BriefDescription": "L2 cache lines filling L2",
64 …"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover …
69 …riefDescription": "Modified cache lines that are evicted by L2 cache when triggered by an L2 cache…
73 …scription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache…
78 …on": "Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache…
82 …": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache…
87 "BriefDescription": "L2 code requests",
91 "PublicDescription": "Counts the total number of L2 code requests.",
[all …]
|
| /linux-6.12.1/tools/perf/pmu-events/arch/x86/emeraldrapids/ |
| D | cache.json | 49 …scription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
53 …nts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand re…
77 "BriefDescription": "L2 cache lines filling L2",
81 …"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover …
86 …riefDescription": "Modified cache lines that are evicted by L2 cache when triggered by an L2 cache…
90 …scription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache…
95 …on": "Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache…
99 …": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache…
104 …"BriefDescription": "Cache lines that have been L2 hardware prefetched but not used by demand acce…
108 …ines that have been prefetched by the L2 hardware prefetcher but not used by demand access when ev…
[all …]
|