Lines Matching full:l2
50 "BriefDescription": "Not rejected writebacks that hit L2 cache",
54 "PublicDescription": "This event counts the number of WB requests that hit L2 cache.",
59 "BriefDescription": "L2 cache lines filling L2",
63 …"PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does…
68 "BriefDescription": "L2 cache lines in E state filling L2",
72 …licDescription": "This event counts the number of L2 cache lines in the Exclusive state filling th…
77 "BriefDescription": "L2 cache lines in I state filling L2",
81 …licDescription": "This event counts the number of L2 cache lines in the Invalidate state filling t…
86 "BriefDescription": "L2 cache lines in S state filling L2",
90 …ublicDescription": "This event counts the number of L2 cache lines in the Shared state filling the…
95 "BriefDescription": "Clean L2 cache lines evicted by demand.",
103 "BriefDescription": "L2 code requests",
107 "PublicDescription": "This event counts the total number of L2 code requests.",
116 …uding requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non reje…
121 "BriefDescription": "Demand requests that miss L2 cache.",
129 "BriefDescription": "Demand requests to L2 cache.",
137 "BriefDescription": "Requests from L2 hardware prefetchers",
141 …"PublicDescription": "This event counts the total number of requests from the L2 hardware prefetch…
146 "BriefDescription": "RFO requests to L2 cache",
150 …event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests in…
155 "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
163 "BriefDescription": "L2 cache misses when fetching instructions.",
171 "BriefDescription": "Demand Data Read requests that hit L2 cache",
175 …ounts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache.",
180 "BriefDescription": "Demand Data Read miss L2, no rejects",
184 …ion": "This event counts the number of demand Data Read requests that miss L2 cache. Only not reje…
189 "BriefDescription": "L2 prefetch requests that hit L2 cache",
193 …ption": "This event counts the number of requests from the L2 hardware prefetchers that hit L2 cac…
198 "BriefDescription": "L2 prefetch requests that miss L2 cache",
202 …tion": "This event counts the number of requests from the L2 hardware prefetchers that miss L2 cac…
207 "BriefDescription": "All requests that miss L2 cache.",
215 "BriefDescription": "All L2 requests.",
223 "BriefDescription": "RFO requests that hit L2 cache.",
231 "BriefDescription": "RFO requests that miss L2 cache.",
239 "BriefDescription": "L2 or L3 HW prefetches that access L2 cache",
243 …"PublicDescription": "This event counts L2 or L3 HW prefetches that access L2 cache including reje…
248 "BriefDescription": "Transactions accessing L2 pipe",
252 …"PublicDescription": "This event counts transactions that access the L2 pipe including snoops, pag…
257 "BriefDescription": "L2 cache accesses when fetching instructions",
261 …"PublicDescription": "This event counts the number of L2 cache accesses when fetching instructions…
266 "BriefDescription": "Demand Data Read requests that access L2 cache",
270 …"PublicDescription": "This event counts Demand Data Read requests that access L2 cache, including …
275 "BriefDescription": "L1D writebacks that access L2 cache",
279 "PublicDescription": "This event counts L1D writebacks that access L2 cache.",
284 "BriefDescription": "L2 fill requests that access L2 cache",
288 "PublicDescription": "This event counts L2 fill requests that access L2 cache.",
293 "BriefDescription": "L2 writebacks that access L2 cache",
297 "PublicDescription": "This event counts L2 writebacks that access L2 cache.",
302 "BriefDescription": "RFO requests that access L2 cache",
306 … "PublicDescription": "This event counts Read for Ownership (RFO) requests that access L2 cache.",
464 "BriefDescription": "Retired load uops with L2 cache hits as data sources.",
471 …": "This event counts retired load uops which data sources were hits in the mid-level (L2) cache.",
476 "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.",
482 … counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting exc…
592 …and prefetch data reads. All Core Data Reads include cacheable Demands and L2 prefetchers (not L3 …
647 …A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction…
658 …A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction…
669 …A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction…
680 …ery cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sendi…
690 …ery cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sendi…
700 …A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction…
720 …A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction…