Lines Matching full:l2
5 …"BriefDescription": "L2 cache requests of non-cacheable type (non-cached data and instructions rea…
11 …"BriefDescription": "L2 cache requests: from hardware prefetchers to prefetch directly into L2 (hi…
17 "BriefDescription": "L2 cache requests: prefetch directly into L2.",
23 "BriefDescription": "L2 cache requests: instruction cache reads.",
29 "BriefDescription": "L2 cache requests: data cache shared reads.",
35 "BriefDescription": "L2 cache requests: data cache stores.",
41 …"BriefDescription": "L2 cache requests: data cache reads including hardware and software prefetch.…
47 …"BriefDescription": "L2 cache requests of common types from L1 data cache (including prefetches).",
53 "BriefDescription": "L2 cache requests of common types not including prefetches.",
59 "BriefDescription": "L2 cache requests of all types.",
65 "BriefDescription": "L2 cache requests: non-coherent, non-cacheable LS sized reads.",
71 "BriefDescription": "L2 cache requests: coherent, non-cacheable LS sized reads.",
83 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: instructio…
89 …Description": "Core to L2 cache requests (not including L2 prefetch) with status: instruction cach…
95 …efDescription": "Core to L2 cache requests (not including L2 prefetch) with status: instruction ca…
101 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for instruction cache h…
107 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for instruction cache a…
113 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache…
119 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data and instructio…
125 …iefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache st…
131 …fDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache read…
137 …iefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache re…
143 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache…
149 … "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data cache hits.",
155 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data and instructio…
161 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data cache access.",
167 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data and instructio…
173 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache and are g…
179 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache and are g…
185 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache and are g…
191 …riefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache but hit in th…
197 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache but hit in …
203 …scription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache but hit in the L3 c…
209 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 as well as the L3…
215 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 as well as the L3…
221 …Description": "L2 prefetches accepted by the L2 pipeline which miss the L2 as well as the L3 cache…
227 "BriefDescription": "L2 cache fills from L3 cache or different L2 cache in the same CCX.",
233 …"BriefDescription": "L2 cache fills from cache of another CCX when the address was in the same NUM…
239 "BriefDescription": "L2 cache fills from either DRAM or MMIO in the same NUMA node.",
245 …"BriefDescription": "L2 cache fills from cache of another CCX when the address was in a different …
251 …"BriefDescription": "L2 cache fills from either DRAM or MMIO in a different NUMA node (same or dif…
257 "BriefDescription": "L2 cache fills from extension memory.",
263 "BriefDescription": "L2 cache fills from all types of data sources.",