x86/haswellx/cache.json

57         "BriefDescription": "Not rejected writebacks that hit L2 cache",
61         "PublicDescription": "Not rejected writebacks that hit L2 cache.",
66         "BriefDescription": "L2 cache lines filling L2",
70 …event counts the number of L2 cache lines brought into the L2 cache.  Lines are filled into the L2…
75         "BriefDescription": "L2 cache lines in E state filling L2",
79         "PublicDescription": "L2 cache lines in E state filling L2.",
84         "BriefDescription": "L2 cache lines in I state filling L2",
88         "PublicDescription": "L2 cache lines in I state filling L2.",
93         "BriefDescription": "L2 cache lines in S state filling L2",
97         "PublicDescription": "L2 cache lines in S state filling L2.",
102         "BriefDescription": "Clean L2 cache lines evicted by demand",
106         "PublicDescription": "Clean L2 cache lines evicted by demand.",
111         "BriefDescription": "Dirty L2 cache lines evicted by demand",
115         "PublicDescription": "Dirty L2 cache lines evicted by demand.",
120         "BriefDescription": "L2 code requests",
124         "PublicDescription": "Counts all L2 code requests.",
134         "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",
139         "BriefDescription": "Demand requests that miss L2 cache",
144         "PublicDescription": "Demand requests that miss L2 cache.",
149         "BriefDescription": "Demand requests to L2 cache",
154         "PublicDescription": "Demand requests to L2 cache.",
159         "BriefDescription": "Requests from L2 hardware prefetchers",
163         "PublicDescription": "Counts all L2 HW prefetcher requests.",
168         "BriefDescription": "RFO requests to L2 cache",
172         "PublicDescription": "Counts all L2 store RFO requests.",
177         "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
181         "PublicDescription": "Number of instruction fetches that hit the L2 cache.",
186         "BriefDescription": "L2 cache misses when fetching instructions",
190         "PublicDescription": "Number of instruction fetches that missed the L2 cache.",
195         "BriefDescription": "Demand Data Read requests that hit L2 cache",
200 …Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache",
205         "BriefDescription": "Demand Data Read miss L2, no rejects",
210         "PublicDescription": "Demand data read requests that missed L2, no rejects.",
215         "BriefDescription": "L2 prefetch requests that hit L2 cache",
219         "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.",
224         "BriefDescription": "L2 prefetch requests that miss L2 cache",
228         "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
233         "BriefDescription": "All requests that miss L2 cache",
238         "PublicDescription": "All requests that missed L2.",
243         "BriefDescription": "All L2 requests",
248         "PublicDescription": "All requests to L2 cache.",
253         "BriefDescription": "RFO requests that hit L2 cache",
257         "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.",
262         "BriefDescription": "RFO requests that miss L2 cache",
266         "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
271         "BriefDescription": "L2 or L3 HW prefetches that access L2 cache",
275         "PublicDescription": "Any MLC or L3 HW prefetch accessing L2, including rejects.",
280         "BriefDescription": "Transactions accessing L2 pipe",
284         "PublicDescription": "Transactions accessing L2 pipe.",
289         "BriefDescription": "L2 cache accesses when fetching instructions",
293         "PublicDescription": "L2 cache accesses when fetching instructions.",
298         "BriefDescription": "Demand Data Read requests that access L2 cache",
302         "PublicDescription": "Demand data read requests that access L2 cache.",
307         "BriefDescription": "L1D writebacks that access L2 cache",
311         "PublicDescription": "L1D writebacks that access L2 cache.",
316         "BriefDescription": "L2 fill requests that access L2 cache",
320         "PublicDescription": "L2 fill requests that access L2 cache.",
325         "BriefDescription": "L2 writebacks that access L2 cache",
329         "PublicDescription": "L2 writebacks that access L2 cache.",
334         "BriefDescription": "RFO requests that access L2 cache",
338         "PublicDescription": "RFO requests that access L2 cache.",
493         "BriefDescription": "Retired load uops with L2 cache hits as data sources.",
504         "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.",
511         "PublicDescription": "Retired load uops missed L2. Unknown data source excluded.",
902         "BriefDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3",
912         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3",