Lines Matching full:l2
23 "BriefDescription": "Demand data cache fills from local L2 cache.",
29 …"BriefDescription": "Demand data cache fills from L3 cache or different L2 cache in the same CCX.",
71 "BriefDescription": "Any data cache fills from local L2 cache.",
77 "BriefDescription": "Any data cache fills from L3 cache or different L2 cache in the same CCX.",
83 …"BriefDescription": "Any data cache fills from local L2 cache or L3 cache or different L2 cache in…
149 …move data to all cache levels except L1) and T2 (move data to all cache levels except L1 and L2).",
191 "BriefDescription": "Software prefetch data cache fills from local L2 cache.",
197 …"BriefDescription": "Software prefetch data cache fills from L3 cache or different L2 cache in the…
239 "BriefDescription": "Hardware prefetch data cache fills from local L2 cache.",
245 …"BriefDescription": "Hardware prefetch data cache fills from L3 cache or different L2 cache in the…
292 …"BriefDescription": "L2 cache requests of non-cacheable type (non-cached data and instructions rea…
298 …"BriefDescription": "L2 cache requests: from hardware prefetchers to prefetch directly into L2 (hi…
304 "BriefDescription": "L2 cache requests: prefetch directly into L2.",
310 …"BriefDescription": "L2 cache requests: data cache state change to writable, check L2 for current …
316 "BriefDescription": "L2 cache requests: instruction cache reads.",
322 "BriefDescription": "L2 cache requests: data cache shared reads.",
328 "BriefDescription": "L2 cache requests: data cache stores.",
334 …"BriefDescription": "L2 cache requests: data cache reads including hardware and software prefetch.…
340 …"BriefDescription": "L2 cache requests of common types from L1 data cache (including prefetches).",
346 "BriefDescription": "L2 cache requests of common types not including prefetches.",
352 "BriefDescription": "L2 cache requests of all types.",
358 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: instructio…
364 …Description": "Core to L2 cache requests (not including L2 prefetch) with status: instruction cach…
370 …efDescription": "Core to L2 cache requests (not including L2 prefetch) with status: instruction ca…
376 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for instruction cache h…
382 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for instruction cache a…
388 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache…
394 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data and instructio…
400 …iefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache st…
406 …fDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache read…
412 …iefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache re…
418 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache…
424 … "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data cache hits.",
430 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data and instructio…
436 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data cache access.",
442 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data and instructio…
448 …scription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2Stream …
454 …riefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2N…
460 …escription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2UpDown…
466 …ion": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2Burst (aggres…
472 …iefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2St…
478 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L…
484 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L…
490 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L…
496 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of all ty…
502 … "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of typ…
508 …tion": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache …
514 …: "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of ty…
520 …L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type …
526 …ion": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache o…
532 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in …
538 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in …
544 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in …
550 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in …
556 …tion": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2St…
562 …escription": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of typ…
568 …ption": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2U…
574 … "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2Burst (a…
580 …scription": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type…
586 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches…
592 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches…
598 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches…
604 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches…
610 "BriefDescription": "Instruction cache lines (64 bytes) fulfilled from the L2 cache."