powerpc/power10/datasource.json

15 …ocessor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss…
40 … "All successful D-Side Load dispatches for this thread that missed in the L2. Since the event hap…
45 …"All successful D-Side Store dispatches for this thread that missed in the L2. Since the event hap…
50 …"BriefDescription": "All successful D-side store dispatches for this thread that were L2 hits. Sin…
55 …uction (demand and prefetch) dispatches for this thread that missed in the L2. Since the event hap…
60 …"BriefDescription": "The processor's instruction cache was reloaded from the local core's L2 due t…
65 …"BriefDescription": "The processor's L1 data cache was reloaded from the local core's L2 due to a …
70 …"BriefDescription": "The processor's instruction cache was reloaded from the local core's L2 due t…
75 …"BriefDescription": "The processor's L1 data cache was reloaded from the local core's L2 due to a …
100 …t dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss…
105 …t dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss…
110 …th data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss…
115 …th data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss…
120 …th data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss…
125 …th data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss…
130 …that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss…
135 …that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss…
140 …sor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss…
145 …ocessor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss…
150 …sor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss…
155 …ocessor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss…
230 …h a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in …
235 …h a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in …
240 …he was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in …
245 …he was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in …
250 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 on the …
255 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 on the same…
260 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 on the …
265 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 on the same…
310 …h a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same ch…
315 …h a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same ch…
320 …he was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same ch…
325 …he was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same ch…
330 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 o…
335 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 on th…
340 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 o…
345 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 on th…
350 …h a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in …
355 …h a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in …
360 …he was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in …
365 …he was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in …
370 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 on the …
375 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 on the same…
380 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 on the …
385 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 on the same…
430 …h a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same ch…
435 …h a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same ch…
440 …he was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same ch…
445 …he was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same ch…
450 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 o…
455 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 on th…
460 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 o…
465 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 on th…
530 …h a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip d…
535 …h a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip d…
540 …he was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip d…
545 …he was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip d…
550 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 from a …
555 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 from a remo…
560 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 from a …
565 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 from a remo…
610 …h a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote …
615 …h a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote …
620 …he was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote …
625 …he was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote …
630 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 f…
635 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from …
640 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 f…
645 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from …
710 …h a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip …
715 …h a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip …
720 …he was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip …
725 …he was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip …
730 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 from a …
735 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 from a dist…
740 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 from a …
745 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 from a dist…
790 …h a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant…
795 …h a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant…
800 …he was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant…
805 …he was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant…
810 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 f…
815 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from …
820 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 f…
825 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from …
890 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 f…
895 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from …
900 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 f…
905 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from …
910 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 f…
915 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from …
920 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 f…
925 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from …
950 …"BriefDescription": "The processor's instruction cache was reloaded from the local core's L2 due t…
955 …"BriefDescription": "The processor's L1 data cache was reloaded from the local core's L2 due to a …
960 …"BriefDescription": "The processor's instruction cache was reloaded from the local core's L2 due t…
965 …"BriefDescription": "The processor's L1 data cache was reloaded from the local core's L2 due to a …
990 …t dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss…
995 …t dispatch conflicts with data NOT in the MEPF state from the local core's L2 due to a demand miss…
1000 …th data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss…
1005 …th data in the MEPF state without dispatch conflicts from the local core's L2 due to a demand miss…
1010 …th data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss…
1015 …th data that had a dispatch conflict on ld-hit-store from the local core's L2 due to a demand miss…
1020 …that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss…
1025 …that had a dispatch conflict other than ld-hit-store from the local core's L2 due to a demand miss…
1030 …sor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss…
1035 …ocessor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss…
1040 …sor's instruction cache was reloaded from a source beyond the local core's L2 due to a demand miss…
1045 …ocessor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss…
1120 …h a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in …
1125 …h a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in …
1130 …he was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in …
1135 …he was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in …
1140 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 on the …
1145 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 on the same…
1150 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 on the …
1155 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 on the same…
1200 …h a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same ch…
1205 …h a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same ch…
1210 …he was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same ch…
1215 …he was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same ch…
1220 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 o…
1225 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 on th…
1230 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 o…
1235 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 on th…
1240 …h a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in …
1245 …h a valid line that was not in the M (exclusive) state from another core's L2 on the same chip in …
1250 …he was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in …
1255 …he was reloaded with a line in the M (exclusive) state from another core's L2 on the same chip in …
1260 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 on the …
1265 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 on the same…
1270 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 on the …
1275 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 on the same…
1320 …h a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same ch…
1325 …h a valid line that was not in the M (exclusive) state from another core's L2 or L3 on the same ch…
1330 …he was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same ch…
1335 …he was reloaded with a line in the M (exclusive) state from another core's L2 or L3 on the same ch…
1340 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 o…
1345 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 on th…
1350 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 o…
1355 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 on th…
1420 …h a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip d…
1425 …h a valid line that was not in the M (exclusive) state from another core's L2 from a remote chip d…
1430 …he was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip d…
1435 …he was reloaded with a line in the M (exclusive) state from another core's L2 from a remote chip d…
1440 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 from a …
1445 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 from a remo…
1450 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 from a …
1455 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 from a remo…
1500 …h a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote …
1505 …h a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a remote …
1510 …he was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote …
1515 …he was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a remote …
1520 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 f…
1525 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from …
1530 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 f…
1535 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from …
1600 …h a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip …
1605 …h a valid line that was not in the M (exclusive) state from another core's L2 from a distant chip …
1610 …he was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip …
1615 …he was reloaded with a line in the M (exclusive) state from another core's L2 from a distant chip …
1620 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 from a …
1625 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 from a dist…
1630 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 from a …
1635 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 from a dist…
1680 …h a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant…
1685 …h a valid line that was not in the M (exclusive) state from another core's L2 or L3 from a distant…
1690 …he was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant…
1695 …he was reloaded with a line in the M (exclusive) state from another core's L2 or L3 from a distant…
1700 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 f…
1705 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from …
1710 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 f…
1715 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from …
1780 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 f…
1785 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from …
1790 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 f…
1795 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from …
1800 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 f…
1805 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from …
1810 …"BriefDescription": "The processor's instruction cache was reloaded from another core's L2 or L3 f…
1815 …"BriefDescription": "The processor's L1 data cache was reloaded from another core's L2 or L3 from …