Lines Matching full:l2
32 …scription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
36 …nts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand re…
60 "BriefDescription": "L2 cache lines filling L2",
64 …"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover …
69 …riefDescription": "Modified cache lines that are evicted by L2 cache when triggered by an L2 cache…
73 …scription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache…
78 …on": "Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache…
82 …": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache…
87 "BriefDescription": "L2 code requests",
91 "PublicDescription": "Counts the total number of L2 code requests.",
96 "BriefDescription": "Demand Data Read access L2 cache",
100 …equests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses …
105 "BriefDescription": "RFO requests to L2 cache",
109 …on": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests in…
114 "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
118 "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
123 "BriefDescription": "L2 cache misses when fetching instructions",
127 "PublicDescription": "Counts L2 cache misses when fetching instructions.",
132 "BriefDescription": "Demand Data Read requests that hit L2 cache",
136 …"Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.",
141 "BriefDescription": "Demand Data Read miss L2 cache",
145 … Data Read requests with true-miss in the L2 cache. True-miss excludes misses that were merged wit…
150 "BriefDescription": "Read requests with true-miss in L2 cache",
154 …quests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged w…
159 "BriefDescription": "All accesses to L2 cache",
163 … requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged wit…
168 "BriefDescription": "RFO requests that hit L2 cache",
172 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
177 "BriefDescription": "RFO requests that miss L2 cache",
181 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
186 "BriefDescription": "SW prefetch requests that hit L2 cache.",
190 …"PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFET…
195 "BriefDescription": "SW prefetch requests that miss L2 cache.",
199 …"PublicDescription": "Counts Software prefetch requests that miss the L2 cache. Accounts for PREFE…
204 "BriefDescription": "L2 writebacks that access L2 cache",
208 "PublicDescription": "Counts L2 writebacks that access L2 cache.",
226 …nership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not includ…
407 "BriefDescription": "Retired load instructions with L2 cache hits as data sources",
413 "PublicDescription": "Counts retired load instructions with L2 cache hits as data sources.",
418 "BriefDescription": "Retired load instructions missed L2 cache as data sources",
424 "PublicDescription": "Counts retired load instructions missed L2 cache as data sources.",
485 …d prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 …
521 …A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction…
531 …A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction…
541 …A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction…
551 …y cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sendi…
560 … transaction is considered to be in the Off-core outstanding state between L2 cache miss and data-…
578 … transaction is considered to be in the Off-core outstanding state between L2 cache miss and trans…