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/linux-6.12.1/drivers/clk/at91/ !
Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
20 #define PLL_MUL(reg, layout) (((reg) >> (layout)->mul_shift) & \
21 (layout)->mul_mask)
23 #define PLL_MUL_MASK(layout) ((layout)->mul_mask)
57 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_prepare() local
58 struct regmap *regmap = pll->regmap; in clk_pll_prepare()
59 const struct clk_pll_layout *layout = pll->layout; in clk_pll_prepare()
61 pll->characteristics; in clk_pll_prepare()
62 u8 id = pll->id; in clk_pll_prepare()
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/linux-6.12.1/Documentation/devicetree/bindings/sound/ !
Dti,pcm512x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Animesh Agarwal <animeshagarwal28@gmail.com>
13 - $ref: dai-common.yaml#
18 - ti,pcm5121
19 - ti,pcm5122
20 - ti,pcm5141
21 - ti,pcm5142
22 - ti,pcm5242
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/linux-6.12.1/drivers/video/fbdev/omap2/omapfb/dss/ !
Ddpi.c1 // SPDX-License-Identifier: GPL-2.0-only
37 struct dss_pll *pll; member
55 /* only used in non-DT mode */
64 * XXX we can't currently use DSI PLL for DPI with OMAP3, as the DSI PLL in dpi_get_pll()
66 * disabled, DISPC clock will be disabled, and TV out will stop. in dpi_get_pll()
132 struct dss_pll *pll; member
155 if (ctx->pck_min >= 100000000) { in dpi_calc_dispc_cb()
163 ctx->dispc_cinfo.lck_div = lckd; in dpi_calc_dispc_cb()
164 ctx->dispc_cinfo.pck_div = pckd; in dpi_calc_dispc_cb()
165 ctx->dispc_cinfo.lck = lck; in dpi_calc_dispc_cb()
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Dhdmi4.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com/
27 #include <sound/omap-hdmi-audio.h>
42 r = pm_runtime_resume_and_get(&hdmi.pdev->dev); in hdmi_runtime_get()
55 r = pm_runtime_put_sync(&hdmi.pdev->dev); in hdmi_runtime_put()
56 WARN_ON(r < 0 && r != -ENOSYS); in hdmi_runtime_put()
97 reg = devm_regulator_get(&hdmi.pdev->dev, "vdda"); in hdmi_init_regulator()
100 if (PTR_ERR(reg) != -EPROBE_DEFER) in hdmi_init_regulator()
161 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res); in hdmi_power_on_full()
163 hdmi_pll_compute(&hdmi.pll, p->pixelclock, &hdmi_cinfo); in hdmi_power_on_full()
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Dhdmi5.c1 // SPDX-License-Identifier: GPL-2.0-only
32 #include <sound/omap-hdmi-audio.h>
46 r = pm_runtime_resume_and_get(&hdmi.pdev->dev); in hdmi_runtime_get()
59 r = pm_runtime_put_sync(&hdmi.pdev->dev); in hdmi_runtime_put()
60 WARN_ON(r < 0 && r != -ENOSYS); in hdmi_runtime_put()
116 reg = devm_regulator_get(&hdmi.pdev->dev, "vdda"); in hdmi_init_regulator()
173 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res); in hdmi_power_on_full()
175 hdmi_pll_compute(&hdmi.pll, p->pixelclock, &hdmi_cinfo); in hdmi_power_on_full()
182 r = dss_pll_enable(&hdmi.pll.pll); in hdmi_power_on_full()
184 DSSERR("Failed to enable PLL\n"); in hdmi_power_on_full()
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Dpll.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #define DSS_SUBSYS_NAME "PLL"
30 int dss_pll_register(struct dss_pll *pll) in dss_pll_register() argument
36 dss_plls[i] = pll; in dss_pll_register()
41 return -EBUSY; in dss_pll_register()
44 void dss_pll_unregister(struct dss_pll *pll) in dss_pll_unregister() argument
49 if (dss_plls[i] == pll) { in dss_pll_unregister()
61 if (dss_plls[i] && strcmp(dss_plls[i]->name, name) == 0) in dss_pll_find()
68 int dss_pll_enable(struct dss_pll *pll) in dss_pll_enable() argument
72 r = clk_prepare_enable(pll->clkin); in dss_pll_enable()
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/linux-6.12.1/drivers/clk/meson/ !
Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0
11 * In the most basic form, a Meson PLL is composed as follows:
13 * PLL
14 * +--------------------------------+
16 * | +--+ |
17 * in >>-----[ /N ]--->| | +-----+ |
18 * | | |------| DCO |---->> out
19 * | +--------->| | +--v--+ |
20 * | | +--+ | |
22 * | +--[ *(M + (F/Fmax) ]<--+ |
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/linux-6.12.1/drivers/clk/keystone/ !
Dpll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PLL clock driver for Keystone devices
6 * Murali Karicheri <m-karicheri2@ti.com>
9 #include <linux/clk-provider.h>
26 * struct clk_pll_data - pll data structure
28 * register of pll controller, else it is in the pll_ctrl0((bit 11-6)
29 * @phy_pllm: Physical address of PLLM in pll controller. Used when
31 * @phy_pll_ctl0: Physical address of PLL ctrl0. This could be that of
32 * Main PLL or any other PLLs in the device such as ARM PLL, DDR PLL
33 * or PA PLL available on keystone2. These PLLs are controlled by
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/linux-6.12.1/drivers/gpu/drm/omapdrm/dss/ !
Ddpi.c1 // SPDX-License-Identifier: GPL-2.0-only
37 struct dss_pll *pll; member
49 /* -----------------------------------------------------------------------------
50 * Clock Handling and PLL
66 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL1_1)) in dpi_get_clk_src_dra7xx()
72 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL1_3)) in dpi_get_clk_src_dra7xx()
74 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL2_3)) in dpi_get_clk_src_dra7xx()
80 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL2_1)) in dpi_get_clk_src_dra7xx()
82 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL1_3)) in dpi_get_clk_src_dra7xx()
95 enum omap_channel channel = dpi->output.dispc_channel; in dpi_get_clk_src()
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Dhdmi5.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
31 #include <sound/omap-hdmi-audio.h>
47 r = pm_runtime_get_sync(&hdmi->pdev->dev); in hdmi_runtime_get()
49 pm_runtime_put_noidle(&hdmi->pdev->dev); in hdmi_runtime_get()
61 r = pm_runtime_put_sync(&hdmi->pdev->dev); in hdmi_runtime_put()
62 WARN_ON(r < 0 && r != -ENOSYS); in hdmi_runtime_put()
68 struct hdmi_wp_data *wp = &hdmi->wp; in hdmi_irq_handler()
91 v = hdmi_read_reg(hdmi->phy.base, HDMI_TXPHY_PAD_CFG_CTRL); in hdmi_irq_handler()
94 hdmi_write_reg(hdmi->phy.base, HDMI_TXPHY_PAD_CFG_CTRL, v); in hdmi_irq_handler()
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Dhdmi4.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com/
27 #include <sound/omap-hdmi-audio.h>
46 r = pm_runtime_get_sync(&hdmi->pdev->dev); in hdmi_runtime_get()
48 pm_runtime_put_noidle(&hdmi->pdev->dev); in hdmi_runtime_get()
60 r = pm_runtime_put_sync(&hdmi->pdev->dev); in hdmi_runtime_put()
61 WARN_ON(r < 0 && r != -ENOSYS); in hdmi_runtime_put()
67 struct hdmi_wp_data *wp = &hdmi->wp; in hdmi_irq_handler()
93 u32 intr4 = hdmi_read_reg(hdmi->core.base, HDMI_CORE_SYS_INTR4); in hdmi_irq_handler()
95 hdmi_write_reg(hdmi->core.base, HDMI_CORE_SYS_INTR4, intr4); in hdmi_irq_handler()
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Dpll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
6 #define DSS_SUBSYS_NAME "PLL"
28 int dss_pll_register(struct dss_device *dss, struct dss_pll *pll) in dss_pll_register() argument
32 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) { in dss_pll_register()
33 if (!dss->plls[i]) { in dss_pll_register()
34 dss->plls[i] = pll; in dss_pll_register()
35 pll->dss = dss; in dss_pll_register()
40 return -EBUSY; in dss_pll_register()
43 void dss_pll_unregister(struct dss_pll *pll) in dss_pll_unregister() argument
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/linux-6.12.1/drivers/clk/tegra/ !
Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
31 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
34 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
37 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
230 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
231 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
232 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
233 #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset)
234 #define pll_readl_sdm_din(p) pll_readl(p->params->sdm_din_reg, p)
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/linux-6.12.1/drivers/clk/analogbits/ !
Dwrpll-cln28hpc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018-2019 SiFive, Inc.
8 * the CLN28HPC variant of the Analog Bits Wide Range PLL. The
10 * integrates this PLL; thus the register structure and programming
16 * pre-determined set of performance points.
19 * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
20 * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
21 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
33 #include <linux/clk/analogbits-wrpll-cln28hpc.h>
41 /* MIN_POST_DIVIDE_REF_FREQ: minimum post-divider reference frequency, in Hz */
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/linux-6.12.1/drivers/clk/mediatek/ !
Dclk-pllfh.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Edward-JW Yang <edward-jw.yang@mediatek.com>
14 #include "clk-mtk.h"
15 #include "clk-pllfh.h"
16 #include "clk-fhctl.h"
22 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); in to_mtk_fh() local
24 return container_of(pll, struct mtk_fh, clk_pll); in to_mtk_fh()
30 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); in mtk_fhctl_set_rate() local
35 mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate); in mtk_fhctl_set_rate()
37 return fh->ops->hopping(fh, pcw, postdiv); in mtk_fhctl_set_rate()
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/linux-6.12.1/drivers/media/i2c/ !
Dccs-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/media/i2c/ccs-pll.c
5 * Generic MIPI CCS/SMIA/SMIA++ PLL calculator
8 * Copyright (C) 2011--2012 Nokia Corporation
17 #include "ccs-pll.h"
55 dev_dbg(dev, "%s_%s out of bounds: %d (%d--%d)\n", prefix, in bounds_check()
58 return -EINVAL; in bounds_check()
78 static void print_pll(struct device *dev, struct ccs_pll *pll) in print_pll() argument
85 { &pll->vt_fr, &pll->vt_bk, PLL_VT }, in print_pll()
86 { &pll->op_fr, &pll->op_bk, PLL_OP } in print_pll()
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/linux-6.12.1/drivers/clk/sophgo/ !
Dclk-sg2042-pll.c1 // SPDX-License-Identifier: GPL-2.0
3 * Sophgo SG2042 PLL clock Driver
12 #include <linux/clk-provider.h>
18 #include <dt-bindings/clock/sophgo,sg2042-pll.h>
20 #include "clk-sg2042.h"
24 #define R_PLL_STAT (0xC0 - R_PLL_BEGIN)
25 #define R_PLL_CLKEN_CONTROL (0xC4 - R_PLL_BEGIN)
26 #define R_MPLL_CONTROL (0xE8 - R_PLL_BEGIN)
27 #define R_FPLL_CONTROL (0xF4 - R_PLL_BEGIN)
28 #define R_DPLL0_CONTROL (0xF8 - R_PLL_BEGIN)
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/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ !
Dgt215.c19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
27 #include "pll.h"
31 #include <subdev/bios/pll.h>
45 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
50 return device->crystal; in read_vco()
63 struct nvkm_device *device = clk->base.subdev.device; in read_clk()
68 if (device->chipset == 0xaf) { in read_clk()
73 return device->crystal; in read_clk()
88 return device->crystal; in read_clk()
108 read_pll(struct gt215_clk *clk, int idx, u32 pll) in read_pll() argument
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Dgk20a.c2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
48 for (pl = 0; pl < ARRAY_SIZE(_pl_to_div) - 1; pl++) { in div_to_pl()
53 return ARRAY_SIZE(_pl_to_div) - 1; in div_to_pl()
65 gk20a_pllg_read_mnp(struct gk20a_clk *clk, struct gk20a_pll *pll) in gk20a_pllg_read_mnp() argument
67 struct nvkm_device *device = clk->base.subdev.device; in gk20a_pllg_read_mnp()
71 pll->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); in gk20a_pllg_read_mnp()
72 pll->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH); in gk20a_pllg_read_mnp()
73 pll->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); in gk20a_pllg_read_mnp()
77 gk20a_pllg_write_mnp(struct gk20a_clk *clk, const struct gk20a_pll *pll) in gk20a_pllg_write_mnp() argument
[all …]
/linux-6.12.1/drivers/gpu/drm/i915/display/ !
Dintel_dpll_mgr.c2 * Copyright © 2006-2016 Intel Corporation
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
45 * per-pipe or per-encoder dedicated PLLs, others allow the use of any PLL
47 * share a PLL if their configurations match.
51 * users of a PLL are tracked and that tracking is integrated with the atomic
64 * Hook for enabling the pll, called from intel_enable_shared_dpll() if
65 * the pll is not already enabled.
68 struct intel_shared_dpll *pll,
72 * Hook for disabling the pll, called from intel_disable_shared_dpll()
73 * only when it is safe to disable the pll, i.e., there are no more
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/linux-6.12.1/drivers/clk/baikal-t1/ !
Dccu-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Baikal-T1 CCU PLL interface driver
12 #define pr_fmt(fmt) "bt1-ccu-pll: " fmt
20 #include <linux/clk-provider.h>
29 #include "ccu-pll.h"
88 static int ccu_pll_reset(struct ccu_pll *pll, unsigned long ref_clk, in ccu_pll_reset() argument
97 regmap_update_bits(pll->sys_regs, pll->reg_ctl, in ccu_pll_reset()
100 return regmap_read_poll_timeout_atomic(pll->sys_regs, pll->reg_ctl, val, in ccu_pll_reset()
107 struct ccu_pll *pll = to_ccu_pll(hw); in ccu_pll_enable() local
114 return -EINVAL; in ccu_pll_enable()
[all …]
/linux-6.12.1/drivers/clk/sunxi-ng/ !
Dccu_common.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Maxime Ripard <maxime.ripard@free-electrons.com>
9 #include <linux/clk-provider.h>
33 if (common->features & CCU_FEATURE_LOCK_REG) in ccu_helper_wait_for_lock()
34 addr = common->base + common->lock_reg; in ccu_helper_wait_for_lock()
36 addr = common->base + common->reg; in ccu_helper_wait_for_lock()
49 clk_hw_get_rate_range(&common->hw, &min_rate, &max_rate); in ccu_is_better_rate()
57 if (common->features & CCU_FEATURE_CLOSEST_RATE) in ccu_is_better_rate()
58 return abs(current_rate - target_rate) < abs(best_rate - target_rate); in ccu_is_better_rate()
65 * This clock notifier is called when the frequency of a PLL clock is
[all …]
/linux-6.12.1/drivers/gpu/drm/stm/ !
Ddw_mipi_dsi-stm.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk-provider.h>
42 #define WISR_PLLLS BIT(8) /* PLL Lock Status */
49 #define DSI_WRPCR 0x0430 /* Wrapper Regulator & Pll Ctrl Reg */
50 #define WRPCR_PLLEN BIT(0) /* PLL ENable */
51 #define WRPCR_NDIV GENMASK(8, 2) /* pll loop DIVision Factor */
52 #define WRPCR_IDF GENMASK(14, 11) /* pll Input Division Factor */
53 #define WRPCR_ODF GENMASK(17, 16) /* pll Output Division Factor */
76 /* Sleep & timeout for regulator on/off, pll lock/unlock & fifo empty */
96 writel(val, dsi->base + reg); in dsi_write()
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/linux-6.12.1/Documentation/devicetree/bindings/clock/ !
Dsilabs,si5341.txt6 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
8 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
10 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
13 clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
21 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
33 - compatible: shall be one of the following:
34 "silabs,si5340" - Si5340 A/B/C/D
35 "silabs,si5341" - Si5341 A/B/C/D
36 "silabs,si5342" - Si5342 A/B/C/D
37 "silabs,si5344" - Si5344 A/B/C/D
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/linux-6.12.1/arch/arm64/boot/dts/sprd/ !
Dsc9860.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
15 #address-cells = <2>;
16 #size-cells = <0>;
18 cpu-map {
52 compatible = "arm,cortex-a53";
54 enable-method = "psci";
55 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
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