2  * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
48 	for (pl = 0; pl < ARRAY_SIZE(_pl_to_div) - 1; pl++) {  in div_to_pl()
53 	return ARRAY_SIZE(_pl_to_div) - 1;  in div_to_pl()
65 gk20a_pllg_read_mnp(struct gk20a_clk *clk, struct gk20a_pll *pll)  in gk20a_pllg_read_mnp()  argument
67 	struct nvkm_device *device = clk->base.subdev.device;  in gk20a_pllg_read_mnp()
71 	pll->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH);  in gk20a_pllg_read_mnp()
72 	pll->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH);  in gk20a_pllg_read_mnp()
73 	pll->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH);  in gk20a_pllg_read_mnp()
77 gk20a_pllg_write_mnp(struct gk20a_clk *clk, const struct gk20a_pll *pll)  in gk20a_pllg_write_mnp()  argument
79 	struct nvkm_device *device = clk->base.subdev.device;  in gk20a_pllg_write_mnp()
82 	val = (pll->m & MASK(GPCPLL_COEFF_M_WIDTH)) << GPCPLL_COEFF_M_SHIFT;  in gk20a_pllg_write_mnp()
83 	val |= (pll->n & MASK(GPCPLL_COEFF_N_WIDTH)) << GPCPLL_COEFF_N_SHIFT;  in gk20a_pllg_write_mnp()
84 	val |= (pll->pl & MASK(GPCPLL_COEFF_P_WIDTH)) << GPCPLL_COEFF_P_SHIFT;  in gk20a_pllg_write_mnp()
89 gk20a_pllg_calc_rate(struct gk20a_clk *clk, struct gk20a_pll *pll)  in gk20a_pllg_calc_rate()  argument
94 	rate = clk->parent_rate * pll->n;  in gk20a_pllg_calc_rate()
95 	divider = pll->m * clk->pl_to_div(pll->pl);  in gk20a_pllg_calc_rate()
102 		    struct gk20a_pll *pll)  in gk20a_pllg_calc_mnp()  argument
104 	struct nvkm_subdev *subdev = &clk->base.subdev;  in gk20a_pllg_calc_mnp()
114 	ref_clk_f = clk->parent_rate / KHZ;  in gk20a_pllg_calc_mnp()
117 	max_vco_f = max(clk->params->max_vco, target_vco_f);  in gk20a_pllg_calc_mnp()
118 	min_vco_f = clk->params->min_vco;  in gk20a_pllg_calc_mnp()
119 	best_m = clk->params->max_m;  in gk20a_pllg_calc_mnp()
120 	best_n = clk->params->min_n;  in gk20a_pllg_calc_mnp()
121 	best_pl = clk->params->min_pl;  in gk20a_pllg_calc_mnp()
124 	high_pl = (max_vco_f + target_vco_f - 1) / target_vco_f;  in gk20a_pllg_calc_mnp()
125 	high_pl = min(high_pl, clk->params->max_pl);  in gk20a_pllg_calc_mnp()
126 	high_pl = max(high_pl, clk->params->min_pl);  in gk20a_pllg_calc_mnp()
127 	high_pl = clk->div_to_pl(high_pl);  in gk20a_pllg_calc_mnp()
131 	low_pl = min(low_pl, clk->params->max_pl);  in gk20a_pllg_calc_mnp()
132 	low_pl = max(low_pl, clk->params->min_pl);  in gk20a_pllg_calc_mnp()
133 	low_pl = clk->div_to_pl(low_pl);  in gk20a_pllg_calc_mnp()
136 		   clk->pl_to_div(low_pl), high_pl, clk->pl_to_div(high_pl));  in gk20a_pllg_calc_mnp()
142 		target_vco_f = target_clk_f * clk->pl_to_div(pl);  in gk20a_pllg_calc_mnp()
144 		for (m = clk->params->min_m; m <= clk->params->max_m; m++) {  in gk20a_pllg_calc_mnp()
147 			if (u_f < clk->params->min_u)  in gk20a_pllg_calc_mnp()
149 			if (u_f > clk->params->max_u)  in gk20a_pllg_calc_mnp()
153 			n2 = ((target_vco_f * m) + (ref_clk_f - 1)) / ref_clk_f;  in gk20a_pllg_calc_mnp()
155 			if (n > clk->params->max_n)  in gk20a_pllg_calc_mnp()
161 				if (n < clk->params->min_n)  in gk20a_pllg_calc_mnp()
163 				if (n > clk->params->max_n)  in gk20a_pllg_calc_mnp()
171 					lwv = (vco_f + (clk->pl_to_div(pl) / 2))  in gk20a_pllg_calc_mnp()
172 						/ clk->pl_to_div(pl);  in gk20a_pllg_calc_mnp()
173 					delta = abs(lwv - target_clk_f);  in gk20a_pllg_calc_mnp()
197 	pll->m = best_m;  in gk20a_pllg_calc_mnp()
198 	pll->n = best_n;  in gk20a_pllg_calc_mnp()
199 	pll->pl = best_pl;  in gk20a_pllg_calc_mnp()
201 	target_freq = gk20a_pllg_calc_rate(clk, pll);  in gk20a_pllg_calc_mnp()
205 		   target_freq / KHZ, pll->m, pll->n, pll->pl,  in gk20a_pllg_calc_mnp()
206 		   clk->pl_to_div(pll->pl));  in gk20a_pllg_calc_mnp()
213 	struct nvkm_subdev *subdev = &clk->base.subdev;  in gk20a_pllg_slide()
214 	struct nvkm_device *device = subdev->device;  in gk20a_pllg_slide()
215 	struct gk20a_pll pll;  in gk20a_pllg_slide()  local
219 	gk20a_pllg_read_mnp(clk, &pll);  in gk20a_pllg_slide()
221 	if (n == pll.n)  in gk20a_pllg_slide()
224 	/* pll slowdown mode */  in gk20a_pllg_slide()
230 	pll.n = n;  in gk20a_pllg_slide()
232 	gk20a_pllg_write_mnp(clk, &pll);  in gk20a_pllg_slide()
244 		ret = -ETIMEDOUT;  in gk20a_pllg_slide()
258 	struct nvkm_device *device = clk->base.subdev.device;  in gk20a_pllg_enable()
274 		return -ETIMEDOUT;  in gk20a_pllg_enable()
286 	struct nvkm_device *device = clk->base.subdev.device;  in gk20a_pllg_disable()
288 	/* put PLL in bypass before disabling it */  in gk20a_pllg_disable()
296 gk20a_pllg_program_mnp(struct gk20a_clk *clk, const struct gk20a_pll *pll)  in gk20a_pllg_program_mnp()  argument
298 	struct nvkm_subdev *subdev = &clk->base.subdev;  in gk20a_pllg_program_mnp()
299 	struct nvkm_device *device = subdev->device;  in gk20a_pllg_program_mnp()
305 	/* split VCO-to-bypass jump in half by setting out divider 1:2 */  in gk20a_pllg_program_mnp()
316 	gk20a_pllg_write_mnp(clk, pll);  in gk20a_pllg_program_mnp()
322 	/* restore out divider 1:1 */  in gk20a_pllg_program_mnp()
335 gk20a_pllg_program_mnp_slide(struct gk20a_clk *clk, const struct gk20a_pll *pll)  in gk20a_pllg_program_mnp_slide()  argument
344 		if (pll->m == cur_pll.m && pll->pl == cur_pll.pl)  in gk20a_pllg_program_mnp_slide()
345 			return gk20a_pllg_slide(clk, pll->n);  in gk20a_pllg_program_mnp_slide()
355 	cur_pll = *pll;  in gk20a_pllg_program_mnp_slide()
362 	return gk20a_pllg_slide(clk, pll->n);  in gk20a_pllg_program_mnp_slide()
463 	struct nvkm_subdev *subdev = &clk->base.subdev;  in gk20a_clk_read()
464 	struct nvkm_device *device = subdev->device;  in gk20a_clk_read()
465 	struct gk20a_pll pll;  in gk20a_clk_read()  local
469 		return device->crystal;  in gk20a_clk_read()
471 		gk20a_pllg_read_mnp(clk, &pll);  in gk20a_clk_read()
472 		return gk20a_pllg_calc_rate(clk, &pll) / GK20A_CLK_GPC_MDIV;  in gk20a_clk_read()
475 		return -EINVAL;  in gk20a_clk_read()
484 	return gk20a_pllg_calc_mnp(clk, cstate->domain[nv_clk_src_gpc] *  in gk20a_clk_calc()
485 					 GK20A_CLK_GPC_MDIV, &clk->pll);  in gk20a_clk_calc()
494 	ret = gk20a_pllg_program_mnp_slide(clk, &clk->pll);  in gk20a_clk_prog()
496 		ret = gk20a_pllg_program_mnp(clk, &clk->pll);  in gk20a_clk_prog()
509 	struct nvkm_subdev *subdev = &clk->base.subdev;  in gk20a_clk_setup_slide()
510 	struct nvkm_device *device = subdev->device;  in gk20a_clk_setup_slide()
513 	switch (clk->parent_rate) {  in gk20a_clk_setup_slide()
530 			   clk->parent_rate / KHZ);  in gk20a_clk_setup_slide()
531 		return -EINVAL;  in gk20a_clk_setup_slide()
545 	struct nvkm_device *device = base->subdev.device;  in gk20a_clk_fini()
550 		struct gk20a_pll pll;  in gk20a_clk_fini()  local
553 		gk20a_pllg_read_mnp(clk, &pll);  in gk20a_clk_fini()
554 		n_lo = gk20a_pllg_n_lo(clk, &pll);  in gk20a_clk_fini()
568 	struct nvkm_subdev *subdev = &clk->base.subdev;  in gk20a_clk_init()
569 	struct nvkm_device *device = subdev->device;  in gk20a_clk_init()
572 	/* get out from IDDQ */  in gk20a_clk_init()
585 	base->func->calc(base, &base->func->pstates[0].base);  in gk20a_clk_init()
586 	ret = base->func->prog(&clk->base);  in gk20a_clk_init()
617 	struct nvkm_device_tegra *tdev = device->func->tegra(device);  in gk20a_clk_ctor()
622 	for (i = 0; i < func->nr_pstates; i++) {  in gk20a_clk_ctor()
623 		INIT_LIST_HEAD(&func->pstates[i].list);  in gk20a_clk_ctor()
624 		func->pstates[i].pstate = i + 1;  in gk20a_clk_ctor()
627 	clk->params = params;  in gk20a_clk_ctor()
628 	clk->parent_rate = clk_get_rate(tdev->clk);  in gk20a_clk_ctor()
630 	ret = nvkm_clk_ctor(func, device, type, inst, true, &clk->base);  in gk20a_clk_ctor()
634 	nvkm_debug(&clk->base.subdev, "parent clock rate: %d Khz\n",  in gk20a_clk_ctor()
635 		   clk->parent_rate / KHZ);  in gk20a_clk_ctor()
649 		return -ENOMEM;  in gk20a_clk_new()
650 	*pclk = &clk->base;  in gk20a_clk_new()
654 	clk->pl_to_div = pl_to_div;  in gk20a_clk_new()
655 	clk->div_to_pl = div_to_pl;  in gk20a_clk_new()