Lines Matching +full:pll +full:- +full:out
2 * Copyright © 2006-2016 Intel Corporation
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
45 * per-pipe or per-encoder dedicated PLLs, others allow the use of any PLL
47 * share a PLL if their configurations match.
51 * users of a PLL are tracked and that tracking is integrated with the atomic
64 * Hook for enabling the pll, called from intel_enable_shared_dpll() if
65 * the pll is not already enabled.
68 struct intel_shared_dpll *pll,
72 * Hook for disabling the pll, called from intel_disable_shared_dpll()
73 * only when it is safe to disable the pll, i.e., there are no more
77 struct intel_shared_dpll *pll);
85 struct intel_shared_dpll *pll,
89 * Hook for calculating the pll's output frequency based on its passed
93 const struct intel_shared_dpll *pll,
122 struct intel_shared_dpll *pll; in intel_atomic_duplicate_dpll_state() local
126 for_each_shared_dpll(i915, pll, i) in intel_atomic_duplicate_dpll_state()
127 shared_dpll[pll->index] = pll->state; in intel_atomic_duplicate_dpll_state()
135 drm_WARN_ON(s->dev, !drm_modeset_is_locked(&s->dev->mode_config.connection_mutex)); in intel_atomic_get_shared_dpll_state()
137 if (!state->dpll_set) { in intel_atomic_get_shared_dpll_state()
138 state->dpll_set = true; in intel_atomic_get_shared_dpll_state()
140 intel_atomic_duplicate_dpll_state(to_i915(s->dev), in intel_atomic_get_shared_dpll_state()
141 state->shared_dpll); in intel_atomic_get_shared_dpll_state()
144 return state->shared_dpll; in intel_atomic_get_shared_dpll_state()
148 * intel_get_shared_dpll_by_id - get a DPLL given its id
150 * @id: pll id
159 struct intel_shared_dpll *pll; in intel_get_shared_dpll_by_id() local
162 for_each_shared_dpll(i915, pll, i) { in intel_get_shared_dpll_by_id()
163 if (pll->info->id == id) in intel_get_shared_dpll_by_id()
164 return pll; in intel_get_shared_dpll_by_id()
173 struct intel_shared_dpll *pll, in assert_shared_dpll() argument
179 if (drm_WARN(&i915->drm, !pll, in assert_shared_dpll()
183 cur_state = intel_dpll_get_hw_state(i915, pll, &hw_state); in assert_shared_dpll()
186 pll->info->name, str_on_off(state), in assert_shared_dpll()
192 return TC_PORT_1 + id - DPLL_ID_ICL_MGPLL1; in icl_pll_id_to_tc_port()
197 return tc_port - TC_PORT_1 + DPLL_ID_ICL_MGPLL1; in icl_tc_port_to_pll_id()
202 struct intel_shared_dpll *pll) in intel_combo_pll_enable_reg() argument
205 return DG1_DPLL_ENABLE(pll->info->id); in intel_combo_pll_enable_reg()
207 (pll->info->id == DPLL_ID_EHL_DPLL4)) in intel_combo_pll_enable_reg()
210 return ICL_DPLL_ENABLE(pll->info->id); in intel_combo_pll_enable_reg()
215 struct intel_shared_dpll *pll) in intel_tc_pll_enable_reg() argument
217 const enum intel_dpll_id id = pll->info->id; in intel_tc_pll_enable_reg()
227 struct intel_shared_dpll *pll) in _intel_enable_shared_dpll() argument
229 if (pll->info->power_domain) in _intel_enable_shared_dpll()
230 pll->wakeref = intel_display_power_get(i915, pll->info->power_domain); in _intel_enable_shared_dpll()
232 pll->info->funcs->enable(i915, pll, &pll->state.hw_state); in _intel_enable_shared_dpll()
233 pll->on = true; in _intel_enable_shared_dpll()
237 struct intel_shared_dpll *pll) in _intel_disable_shared_dpll() argument
239 pll->info->funcs->disable(i915, pll); in _intel_disable_shared_dpll()
240 pll->on = false; in _intel_disable_shared_dpll()
242 if (pll->info->power_domain) in _intel_disable_shared_dpll()
243 intel_display_power_put(i915, pll->info->power_domain, pll->wakeref); in _intel_disable_shared_dpll()
247 * intel_enable_shared_dpll - enable a CRTC's shared DPLL
254 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_enable_shared_dpll()
255 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_enable_shared_dpll()
256 struct intel_shared_dpll *pll = crtc_state->shared_dpll; in intel_enable_shared_dpll() local
257 unsigned int pipe_mask = BIT(crtc->pipe); in intel_enable_shared_dpll()
260 if (drm_WARN_ON(&i915->drm, pll == NULL)) in intel_enable_shared_dpll()
263 mutex_lock(&i915->display.dpll.lock); in intel_enable_shared_dpll()
264 old_mask = pll->active_mask; in intel_enable_shared_dpll()
266 if (drm_WARN_ON(&i915->drm, !(pll->state.pipe_mask & pipe_mask)) || in intel_enable_shared_dpll()
267 drm_WARN_ON(&i915->drm, pll->active_mask & pipe_mask)) in intel_enable_shared_dpll()
268 goto out; in intel_enable_shared_dpll()
270 pll->active_mask |= pipe_mask; in intel_enable_shared_dpll()
272 drm_dbg_kms(&i915->drm, in intel_enable_shared_dpll()
274 pll->info->name, pll->active_mask, pll->on, in intel_enable_shared_dpll()
275 crtc->base.base.id, crtc->base.name); in intel_enable_shared_dpll()
278 drm_WARN_ON(&i915->drm, !pll->on); in intel_enable_shared_dpll()
279 assert_shared_dpll_enabled(i915, pll); in intel_enable_shared_dpll()
280 goto out; in intel_enable_shared_dpll()
282 drm_WARN_ON(&i915->drm, pll->on); in intel_enable_shared_dpll()
284 drm_dbg_kms(&i915->drm, "enabling %s\n", pll->info->name); in intel_enable_shared_dpll()
286 _intel_enable_shared_dpll(i915, pll); in intel_enable_shared_dpll()
288 out: in intel_enable_shared_dpll()
289 mutex_unlock(&i915->display.dpll.lock); in intel_enable_shared_dpll()
293 * intel_disable_shared_dpll - disable a CRTC's shared DPLL
300 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_disable_shared_dpll()
301 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_disable_shared_dpll()
302 struct intel_shared_dpll *pll = crtc_state->shared_dpll; in intel_disable_shared_dpll() local
303 unsigned int pipe_mask = BIT(crtc->pipe); in intel_disable_shared_dpll()
309 if (pll == NULL) in intel_disable_shared_dpll()
312 mutex_lock(&i915->display.dpll.lock); in intel_disable_shared_dpll()
313 if (drm_WARN(&i915->drm, !(pll->active_mask & pipe_mask), in intel_disable_shared_dpll()
314 "%s not used by [CRTC:%d:%s]\n", pll->info->name, in intel_disable_shared_dpll()
315 crtc->base.base.id, crtc->base.name)) in intel_disable_shared_dpll()
316 goto out; in intel_disable_shared_dpll()
318 drm_dbg_kms(&i915->drm, in intel_disable_shared_dpll()
320 pll->info->name, pll->active_mask, pll->on, in intel_disable_shared_dpll()
321 crtc->base.base.id, crtc->base.name); in intel_disable_shared_dpll()
323 assert_shared_dpll_enabled(i915, pll); in intel_disable_shared_dpll()
324 drm_WARN_ON(&i915->drm, !pll->on); in intel_disable_shared_dpll()
326 pll->active_mask &= ~pipe_mask; in intel_disable_shared_dpll()
327 if (pll->active_mask) in intel_disable_shared_dpll()
328 goto out; in intel_disable_shared_dpll()
330 drm_dbg_kms(&i915->drm, "disabling %s\n", pll->info->name); in intel_disable_shared_dpll()
332 _intel_disable_shared_dpll(i915, pll); in intel_disable_shared_dpll()
334 out: in intel_disable_shared_dpll()
335 mutex_unlock(&i915->display.dpll.lock); in intel_disable_shared_dpll()
341 struct intel_shared_dpll *pll; in intel_dpll_mask_all() local
345 for_each_shared_dpll(i915, pll, i) { in intel_dpll_mask_all()
346 drm_WARN_ON(&i915->drm, dpll_mask & BIT(pll->info->id)); in intel_dpll_mask_all()
348 dpll_mask |= BIT(pll->info->id); in intel_dpll_mask_all()
360 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_find_shared_dpll()
366 shared_dpll = intel_atomic_get_shared_dpll_state(&state->base); in intel_find_shared_dpll()
368 drm_WARN_ON(&i915->drm, dpll_mask & ~dpll_mask_all); in intel_find_shared_dpll()
371 struct intel_shared_dpll *pll; in intel_find_shared_dpll() local
373 pll = intel_get_shared_dpll_by_id(i915, id); in intel_find_shared_dpll()
374 if (!pll) in intel_find_shared_dpll()
378 if (shared_dpll[pll->index].pipe_mask == 0) { in intel_find_shared_dpll()
380 unused_pll = pll; in intel_find_shared_dpll()
385 &shared_dpll[pll->index].hw_state, in intel_find_shared_dpll()
387 drm_dbg_kms(&i915->drm, in intel_find_shared_dpll()
389 crtc->base.base.id, crtc->base.name, in intel_find_shared_dpll()
390 pll->info->name, in intel_find_shared_dpll()
391 shared_dpll[pll->index].pipe_mask, in intel_find_shared_dpll()
392 pll->active_mask); in intel_find_shared_dpll()
393 return pll; in intel_find_shared_dpll()
399 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] allocated %s\n", in intel_find_shared_dpll()
400 crtc->base.base.id, crtc->base.name, in intel_find_shared_dpll()
401 unused_pll->info->name); in intel_find_shared_dpll()
409 * intel_reference_shared_dpll_crtc - Get a DPLL reference for a CRTC
411 * @pll: DPLL for which the reference is taken
414 * Take a reference for @pll tracking the use of it by @crtc.
418 const struct intel_shared_dpll *pll, in intel_reference_shared_dpll_crtc() argument
421 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_reference_shared_dpll_crtc()
423 drm_WARN_ON(&i915->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) != 0); in intel_reference_shared_dpll_crtc()
425 shared_dpll_state->pipe_mask |= BIT(crtc->pipe); in intel_reference_shared_dpll_crtc()
427 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] reserving %s\n", in intel_reference_shared_dpll_crtc()
428 crtc->base.base.id, crtc->base.name, pll->info->name); in intel_reference_shared_dpll_crtc()
434 const struct intel_shared_dpll *pll, in intel_reference_shared_dpll() argument
439 shared_dpll = intel_atomic_get_shared_dpll_state(&state->base); in intel_reference_shared_dpll()
441 if (shared_dpll[pll->index].pipe_mask == 0) in intel_reference_shared_dpll()
442 shared_dpll[pll->index].hw_state = *dpll_hw_state; in intel_reference_shared_dpll()
444 intel_reference_shared_dpll_crtc(crtc, pll, &shared_dpll[pll->index]); in intel_reference_shared_dpll()
448 * intel_unreference_shared_dpll_crtc - Drop a DPLL reference for a CRTC
450 * @pll: DPLL for which the reference is dropped
453 * Drop a reference for @pll tracking the end of use of it by @crtc.
457 const struct intel_shared_dpll *pll, in intel_unreference_shared_dpll_crtc() argument
460 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_unreference_shared_dpll_crtc()
462 drm_WARN_ON(&i915->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) == 0); in intel_unreference_shared_dpll_crtc()
464 shared_dpll_state->pipe_mask &= ~BIT(crtc->pipe); in intel_unreference_shared_dpll_crtc()
466 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] releasing %s\n", in intel_unreference_shared_dpll_crtc()
467 crtc->base.base.id, crtc->base.name, pll->info->name); in intel_unreference_shared_dpll_crtc()
472 const struct intel_shared_dpll *pll) in intel_unreference_shared_dpll() argument
476 shared_dpll = intel_atomic_get_shared_dpll_state(&state->base); in intel_unreference_shared_dpll()
478 intel_unreference_shared_dpll_crtc(crtc, pll, &shared_dpll[pll->index]); in intel_unreference_shared_dpll()
489 new_crtc_state->shared_dpll = NULL; in intel_put_dpll()
491 if (!old_crtc_state->shared_dpll) in intel_put_dpll()
494 intel_unreference_shared_dpll(state, crtc, old_crtc_state->shared_dpll); in intel_put_dpll()
498 * intel_shared_dpll_swap_state - make atomic DPLL configuration effective
502 * helper does not handle driver-specific global state.
510 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_shared_dpll_swap_state()
511 struct intel_shared_dpll_state *shared_dpll = state->shared_dpll; in intel_shared_dpll_swap_state()
512 struct intel_shared_dpll *pll; in intel_shared_dpll_swap_state() local
515 if (!state->dpll_set) in intel_shared_dpll_swap_state()
518 for_each_shared_dpll(i915, pll, i) in intel_shared_dpll_swap_state()
519 swap(pll->state, shared_dpll[pll->index]); in intel_shared_dpll_swap_state()
523 struct intel_shared_dpll *pll, in ibx_pch_dpll_get_hw_state() argument
526 struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx; in ibx_pch_dpll_get_hw_state()
527 const enum intel_dpll_id id = pll->info->id; in ibx_pch_dpll_get_hw_state()
537 hw_state->dpll = val; in ibx_pch_dpll_get_hw_state()
538 hw_state->fp0 = intel_de_read(i915, PCH_FP0(id)); in ibx_pch_dpll_get_hw_state()
539 hw_state->fp1 = intel_de_read(i915, PCH_FP1(id)); in ibx_pch_dpll_get_hw_state()
559 struct intel_shared_dpll *pll, in ibx_pch_dpll_enable() argument
562 const struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx; in ibx_pch_dpll_enable()
563 const enum intel_dpll_id id = pll->info->id; in ibx_pch_dpll_enable()
568 intel_de_write(i915, PCH_FP0(id), hw_state->fp0); in ibx_pch_dpll_enable()
569 intel_de_write(i915, PCH_FP1(id), hw_state->fp1); in ibx_pch_dpll_enable()
571 intel_de_write(i915, PCH_DPLL(id), hw_state->dpll); in ibx_pch_dpll_enable()
582 intel_de_write(i915, PCH_DPLL(id), hw_state->dpll); in ibx_pch_dpll_enable()
588 struct intel_shared_dpll *pll) in ibx_pch_dpll_disable() argument
590 const enum intel_dpll_id id = pll->info->id; in ibx_pch_dpll_disable()
610 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in ibx_get_dpll()
611 struct intel_shared_dpll *pll; in ibx_get_dpll() local
615 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ in ibx_get_dpll()
616 id = (enum intel_dpll_id) crtc->pipe; in ibx_get_dpll()
617 pll = intel_get_shared_dpll_by_id(i915, id); in ibx_get_dpll()
619 drm_dbg_kms(&i915->drm, in ibx_get_dpll()
620 "[CRTC:%d:%s] using pre-allocated %s\n", in ibx_get_dpll()
621 crtc->base.base.id, crtc->base.name, in ibx_get_dpll()
622 pll->info->name); in ibx_get_dpll()
624 pll = intel_find_shared_dpll(state, crtc, in ibx_get_dpll()
625 &crtc_state->dpll_hw_state, in ibx_get_dpll()
630 if (!pll) in ibx_get_dpll()
631 return -EINVAL; in ibx_get_dpll()
633 /* reference the pll */ in ibx_get_dpll()
635 pll, &crtc_state->dpll_hw_state); in ibx_get_dpll()
637 crtc_state->shared_dpll = pll; in ibx_get_dpll()
645 const struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx; in ibx_dump_hw_state()
649 hw_state->dpll, in ibx_dump_hw_state()
650 hw_state->dpll_md, in ibx_dump_hw_state()
651 hw_state->fp0, in ibx_dump_hw_state()
652 hw_state->fp1); in ibx_dump_hw_state()
658 const struct i9xx_dpll_hw_state *a = &_a->i9xx; in ibx_compare_hw_state()
659 const struct i9xx_dpll_hw_state *b = &_b->i9xx; in ibx_compare_hw_state()
661 return a->dpll == b->dpll && in ibx_compare_hw_state()
662 a->dpll_md == b->dpll_md && in ibx_compare_hw_state()
663 a->fp0 == b->fp0 && in ibx_compare_hw_state()
664 a->fp1 == b->fp1; in ibx_compare_hw_state()
689 struct intel_shared_dpll *pll, in hsw_ddi_wrpll_enable() argument
692 const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; in hsw_ddi_wrpll_enable()
693 const enum intel_dpll_id id = pll->info->id; in hsw_ddi_wrpll_enable()
695 intel_de_write(i915, WRPLL_CTL(id), hw_state->wrpll); in hsw_ddi_wrpll_enable()
701 struct intel_shared_dpll *pll, in hsw_ddi_spll_enable() argument
704 const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; in hsw_ddi_spll_enable()
706 intel_de_write(i915, SPLL_CTL, hw_state->spll); in hsw_ddi_spll_enable()
712 struct intel_shared_dpll *pll) in hsw_ddi_wrpll_disable() argument
714 const enum intel_dpll_id id = pll->info->id; in hsw_ddi_wrpll_disable()
723 if (i915->display.dpll.pch_ssc_use & BIT(id)) in hsw_ddi_wrpll_disable()
728 struct intel_shared_dpll *pll) in hsw_ddi_spll_disable() argument
730 enum intel_dpll_id id = pll->info->id; in hsw_ddi_spll_disable()
739 if (i915->display.dpll.pch_ssc_use & BIT(id)) in hsw_ddi_spll_disable()
744 struct intel_shared_dpll *pll, in hsw_ddi_wrpll_get_hw_state() argument
747 struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; in hsw_ddi_wrpll_get_hw_state()
748 const enum intel_dpll_id id = pll->info->id; in hsw_ddi_wrpll_get_hw_state()
758 hw_state->wrpll = val; in hsw_ddi_wrpll_get_hw_state()
766 struct intel_shared_dpll *pll, in hsw_ddi_spll_get_hw_state() argument
769 struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; in hsw_ddi_spll_get_hw_state()
779 hw_state->spll = val; in hsw_ddi_spll_get_hw_state()
793 /* Constraints for PLL good behavior */
875 if (best->p == 0) { in hsw_wrpll_update_rnp()
876 best->p = p; in hsw_wrpll_update_rnp()
877 best->n2 = n2; in hsw_wrpll_update_rnp()
878 best->r2 = r2; in hsw_wrpll_update_rnp()
887 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) / in hsw_wrpll_update_rnp()
892 * If the discrepancy is above the PPM-based budget, always prefer to in hsw_wrpll_update_rnp()
897 b = freq2k * budget * best->p * best->r2; in hsw_wrpll_update_rnp()
899 diff_best = abs_diff(freq2k * best->p * best->r2, in hsw_wrpll_update_rnp()
900 LC_FREQ_2K * best->n2); in hsw_wrpll_update_rnp()
906 if (best->p * best->r2 * diff < p * r2 * diff_best) { in hsw_wrpll_update_rnp()
907 best->p = p; in hsw_wrpll_update_rnp()
908 best->n2 = n2; in hsw_wrpll_update_rnp()
909 best->r2 = r2; in hsw_wrpll_update_rnp()
913 best->p = p; in hsw_wrpll_update_rnp()
914 best->n2 = n2; in hsw_wrpll_update_rnp()
915 best->r2 = r2; in hsw_wrpll_update_rnp()
918 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) { in hsw_wrpll_update_rnp()
919 best->p = p; in hsw_wrpll_update_rnp()
920 best->n2 = n2; in hsw_wrpll_update_rnp()
921 best->r2 = r2; in hsw_wrpll_update_rnp()
940 /* Special case handling for 540 pixel clock: bypass WR PLL entirely in hsw_ddi_calculate_wrpll()
941 * and directly pass the LC PLL to it. */ in hsw_ddi_calculate_wrpll()
951 * the WR PLL. in hsw_ddi_calculate_wrpll()
993 const struct intel_shared_dpll *pll, in hsw_ddi_wrpll_get_freq() argument
996 const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; in hsw_ddi_wrpll_get_freq()
999 u32 wrpll = hw_state->wrpll; in hsw_ddi_wrpll_get_freq()
1003 /* Muxed-SSC for BDW, non-SSC for non-ULT HSW. */ in hsw_ddi_wrpll_get_freq()
1005 refclk = i915->display.dpll.ref_clks.nssc; in hsw_ddi_wrpll_get_freq()
1015 refclk = i915->display.dpll.ref_clks.ssc; in hsw_ddi_wrpll_get_freq()
1037 struct drm_i915_private *i915 = to_i915(state->base.dev); in hsw_ddi_wrpll_compute_dpll()
1040 struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw; in hsw_ddi_wrpll_compute_dpll()
1043 hsw_ddi_calculate_wrpll(crtc_state->port_clock * 1000, &r2, &n2, &p); in hsw_ddi_wrpll_compute_dpll()
1045 hw_state->wrpll = in hsw_ddi_wrpll_compute_dpll()
1050 crtc_state->port_clock = hsw_ddi_wrpll_get_freq(i915, NULL, in hsw_ddi_wrpll_compute_dpll()
1051 &crtc_state->dpll_hw_state); in hsw_ddi_wrpll_compute_dpll()
1064 &crtc_state->dpll_hw_state, in hsw_ddi_wrpll_get_dpll()
1072 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in hsw_ddi_lcpll_compute_dpll()
1073 int clock = crtc_state->port_clock; in hsw_ddi_lcpll_compute_dpll()
1081 drm_dbg_kms(&i915->drm, "Invalid clock for DP: %d\n", in hsw_ddi_lcpll_compute_dpll()
1083 return -EINVAL; in hsw_ddi_lcpll_compute_dpll()
1090 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in hsw_ddi_lcpll_get_dpll()
1091 struct intel_shared_dpll *pll; in hsw_ddi_lcpll_get_dpll() local
1093 int clock = crtc_state->port_clock; in hsw_ddi_lcpll_get_dpll()
1110 pll = intel_get_shared_dpll_by_id(i915, pll_id); in hsw_ddi_lcpll_get_dpll()
1112 if (!pll) in hsw_ddi_lcpll_get_dpll()
1115 return pll; in hsw_ddi_lcpll_get_dpll()
1119 const struct intel_shared_dpll *pll, in hsw_ddi_lcpll_get_freq() argument
1124 switch (pll->info->id) { in hsw_ddi_lcpll_get_freq()
1135 drm_WARN(&i915->drm, 1, "bad port clock sel\n"); in hsw_ddi_lcpll_get_freq()
1148 struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw; in hsw_ddi_spll_compute_dpll()
1150 if (drm_WARN_ON(crtc->base.dev, crtc_state->port_clock / 2 != 135000)) in hsw_ddi_spll_compute_dpll()
1151 return -EINVAL; in hsw_ddi_spll_compute_dpll()
1153 hw_state->spll = in hsw_ddi_spll_compute_dpll()
1166 return intel_find_shared_dpll(state, crtc, &crtc_state->dpll_hw_state, in hsw_ddi_spll_get_dpll()
1171 const struct intel_shared_dpll *pll, in hsw_ddi_spll_get_freq() argument
1174 const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; in hsw_ddi_spll_get_freq()
1177 switch (hw_state->spll & SPLL_FREQ_MASK) { in hsw_ddi_spll_get_freq()
1188 drm_WARN(&i915->drm, 1, "bad spll freq\n"); in hsw_ddi_spll_get_freq()
1209 return -EINVAL; in hsw_compute_dpll()
1218 struct intel_shared_dpll *pll = NULL; in hsw_get_dpll() local
1221 pll = hsw_ddi_wrpll_get_dpll(state, crtc); in hsw_get_dpll()
1223 pll = hsw_ddi_lcpll_get_dpll(crtc_state); in hsw_get_dpll()
1225 pll = hsw_ddi_spll_get_dpll(state, crtc); in hsw_get_dpll()
1227 if (!pll) in hsw_get_dpll()
1228 return -EINVAL; in hsw_get_dpll()
1231 pll, &crtc_state->dpll_hw_state); in hsw_get_dpll()
1233 crtc_state->shared_dpll = pll; in hsw_get_dpll()
1240 i915->display.dpll.ref_clks.ssc = 135000; in hsw_update_dpll_ref_clks()
1241 /* Non-SSC is only used on non-ULT HSW. */ in hsw_update_dpll_ref_clks()
1243 i915->display.dpll.ref_clks.nssc = 24000; in hsw_update_dpll_ref_clks()
1245 i915->display.dpll.ref_clks.nssc = 135000; in hsw_update_dpll_ref_clks()
1251 const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; in hsw_dump_hw_state()
1254 hw_state->wrpll, hw_state->spll); in hsw_dump_hw_state()
1260 const struct hsw_dpll_hw_state *a = &_a->hsw; in hsw_compare_hw_state()
1261 const struct hsw_dpll_hw_state *b = &_b->hsw; in hsw_compare_hw_state()
1263 return a->wrpll == b->wrpll && in hsw_compare_hw_state()
1264 a->spll == b->spll; in hsw_compare_hw_state()
1282 struct intel_shared_dpll *pll, in hsw_ddi_lcpll_enable() argument
1288 struct intel_shared_dpll *pll) in hsw_ddi_lcpll_disable() argument
1293 struct intel_shared_dpll *pll, in hsw_ddi_lcpll_get_hw_state() argument
1333 /* this array is indexed by the *shared* pll id */
1361 struct intel_shared_dpll *pll, in skl_ddi_pll_write_ctrl1() argument
1364 const enum intel_dpll_id id = pll->info->id; in skl_ddi_pll_write_ctrl1()
1370 hw_state->ctrl1 << (id * 6)); in skl_ddi_pll_write_ctrl1()
1375 struct intel_shared_dpll *pll, in skl_ddi_pll_enable() argument
1378 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_ddi_pll_enable()
1380 const enum intel_dpll_id id = pll->info->id; in skl_ddi_pll_enable()
1382 skl_ddi_pll_write_ctrl1(i915, pll, hw_state); in skl_ddi_pll_enable()
1384 intel_de_write(i915, regs[id].cfgcr1, hw_state->cfgcr1); in skl_ddi_pll_enable()
1385 intel_de_write(i915, regs[id].cfgcr2, hw_state->cfgcr2); in skl_ddi_pll_enable()
1393 drm_err(&i915->drm, "DPLL %d not locked\n", id); in skl_ddi_pll_enable()
1397 struct intel_shared_dpll *pll, in skl_ddi_dpll0_enable() argument
1400 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_ddi_dpll0_enable()
1402 skl_ddi_pll_write_ctrl1(i915, pll, hw_state); in skl_ddi_dpll0_enable()
1406 struct intel_shared_dpll *pll) in skl_ddi_pll_disable() argument
1409 const enum intel_dpll_id id = pll->info->id; in skl_ddi_pll_disable()
1417 struct intel_shared_dpll *pll) in skl_ddi_dpll0_disable() argument
1422 struct intel_shared_dpll *pll, in skl_ddi_pll_get_hw_state() argument
1425 struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_ddi_pll_get_hw_state()
1427 const enum intel_dpll_id id = pll->info->id; in skl_ddi_pll_get_hw_state()
1441 goto out; in skl_ddi_pll_get_hw_state()
1444 hw_state->ctrl1 = (val >> (id * 6)) & 0x3f; in skl_ddi_pll_get_hw_state()
1448 hw_state->cfgcr1 = intel_de_read(i915, regs[id].cfgcr1); in skl_ddi_pll_get_hw_state()
1449 hw_state->cfgcr2 = intel_de_read(i915, regs[id].cfgcr2); in skl_ddi_pll_get_hw_state()
1453 out: in skl_ddi_pll_get_hw_state()
1460 struct intel_shared_dpll *pll, in skl_ddi_dpll0_get_hw_state() argument
1463 struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_ddi_dpll0_get_hw_state()
1465 const enum intel_dpll_id id = pll->info->id; in skl_ddi_dpll0_get_hw_state()
1479 if (drm_WARN_ON(&i915->drm, !(val & LCPLL_PLL_ENABLE))) in skl_ddi_dpll0_get_hw_state()
1480 goto out; in skl_ddi_dpll0_get_hw_state()
1483 hw_state->ctrl1 = (val >> (id * 6)) & 0x3f; in skl_ddi_dpll0_get_hw_state()
1487 out: in skl_ddi_dpll0_get_hw_state()
1500 /* DCO freq must be within +1%/-6% of the DCO central freq */
1517 deviation < ctx->min_deviation) { in skl_wrpll_try_divider()
1518 ctx->min_deviation = deviation; in skl_wrpll_try_divider()
1519 ctx->central_freq = central_freq; in skl_wrpll_try_divider()
1520 ctx->dco_freq = dco_freq; in skl_wrpll_try_divider()
1521 ctx->p = divider; in skl_wrpll_try_divider()
1525 deviation < ctx->min_deviation) { in skl_wrpll_try_divider()
1526 ctx->min_deviation = deviation; in skl_wrpll_try_divider()
1527 ctx->central_freq = central_freq; in skl_wrpll_try_divider()
1528 ctx->dco_freq = dco_freq; in skl_wrpll_try_divider()
1529 ctx->p = divider; in skl_wrpll_try_divider()
1534 unsigned int *p0 /* out */, in skl_wrpll_get_multipliers()
1535 unsigned int *p1 /* out */, in skl_wrpll_get_multipliers()
1536 unsigned int *p2 /* out */) in skl_wrpll_get_multipliers()
1602 params->central_freq = 0; in skl_wrpll_params_populate()
1605 params->central_freq = 1; in skl_wrpll_params_populate()
1608 params->central_freq = 3; in skl_wrpll_params_populate()
1613 params->pdiv = 0; in skl_wrpll_params_populate()
1616 params->pdiv = 1; in skl_wrpll_params_populate()
1619 params->pdiv = 2; in skl_wrpll_params_populate()
1622 params->pdiv = 4; in skl_wrpll_params_populate()
1630 params->kdiv = 0; in skl_wrpll_params_populate()
1633 params->kdiv = 1; in skl_wrpll_params_populate()
1636 params->kdiv = 2; in skl_wrpll_params_populate()
1639 params->kdiv = 3; in skl_wrpll_params_populate()
1645 params->qdiv_ratio = p1; in skl_wrpll_params_populate()
1646 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1; in skl_wrpll_params_populate()
1654 params->dco_integer = div_u64(dco_freq, ref_clock * KHz(1)); in skl_wrpll_params_populate()
1655 params->dco_fraction = in skl_wrpll_params_populate()
1656 div_u64((div_u64(dco_freq, ref_clock / KHz(1)) - in skl_wrpll_params_populate()
1657 params->dco_integer * MHz(1)) * 0x8000, MHz(1)); in skl_wrpll_params_populate()
1718 return -EINVAL; in skl_ddi_calculate_wrpll()
1733 const struct intel_shared_dpll *pll, in skl_ddi_wrpll_get_freq() argument
1736 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_ddi_wrpll_get_freq()
1737 int ref_clock = i915->display.dpll.ref_clks.nssc; in skl_ddi_wrpll_get_freq()
1740 p0 = hw_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK; in skl_ddi_wrpll_get_freq()
1741 p2 = hw_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK; in skl_ddi_wrpll_get_freq()
1743 if (hw_state->cfgcr2 & DPLL_CFGCR2_QDIV_MODE(1)) in skl_ddi_wrpll_get_freq()
1744 p1 = (hw_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8; in skl_ddi_wrpll_get_freq()
1761 * Incorrect ASUS-Z170M BIOS setting, the HW seems to ignore bit#0, in skl_ddi_wrpll_get_freq()
1764 drm_dbg_kms(&i915->drm, "Invalid WRPLL PDIV divider value, fixing it.\n"); in skl_ddi_wrpll_get_freq()
1792 dco_freq = (hw_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK) * in skl_ddi_wrpll_get_freq()
1795 dco_freq += ((hw_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * in skl_ddi_wrpll_get_freq()
1798 if (drm_WARN_ON(&i915->drm, p0 == 0 || p1 == 0 || p2 == 0)) in skl_ddi_wrpll_get_freq()
1806 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in skl_ddi_hdmi_pll_dividers()
1807 struct skl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.skl; in skl_ddi_hdmi_pll_dividers()
1811 ret = skl_ddi_calculate_wrpll(crtc_state->port_clock, in skl_ddi_hdmi_pll_dividers()
1812 i915->display.dpll.ref_clks.nssc, &wrpll_params); in skl_ddi_hdmi_pll_dividers()
1820 hw_state->ctrl1 = in skl_ddi_hdmi_pll_dividers()
1824 hw_state->cfgcr1 = in skl_ddi_hdmi_pll_dividers()
1829 hw_state->cfgcr2 = in skl_ddi_hdmi_pll_dividers()
1836 crtc_state->port_clock = skl_ddi_wrpll_get_freq(i915, NULL, in skl_ddi_hdmi_pll_dividers()
1837 &crtc_state->dpll_hw_state); in skl_ddi_hdmi_pll_dividers()
1845 struct skl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.skl; in skl_ddi_dp_set_dpll_hw_state()
1853 switch (crtc_state->port_clock / 2) { in skl_ddi_dp_set_dpll_hw_state()
1875 hw_state->ctrl1 = ctrl1; in skl_ddi_dp_set_dpll_hw_state()
1881 const struct intel_shared_dpll *pll, in skl_ddi_lcpll_get_freq() argument
1884 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_ddi_lcpll_get_freq()
1887 switch ((hw_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0)) >> in skl_ddi_lcpll_get_freq()
1908 drm_WARN(&i915->drm, 1, "Unsupported link rate\n"); in skl_ddi_lcpll_get_freq()
1927 return -EINVAL; in skl_compute_dpll()
1936 struct intel_shared_dpll *pll; in skl_get_dpll() local
1939 pll = intel_find_shared_dpll(state, crtc, in skl_get_dpll()
1940 &crtc_state->dpll_hw_state, in skl_get_dpll()
1943 pll = intel_find_shared_dpll(state, crtc, in skl_get_dpll()
1944 &crtc_state->dpll_hw_state, in skl_get_dpll()
1948 if (!pll) in skl_get_dpll()
1949 return -EINVAL; in skl_get_dpll()
1952 pll, &crtc_state->dpll_hw_state); in skl_get_dpll()
1954 crtc_state->shared_dpll = pll; in skl_get_dpll()
1960 const struct intel_shared_dpll *pll, in skl_ddi_pll_get_freq() argument
1963 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_ddi_pll_get_freq()
1966 * ctrl1 register is already shifted for each pll, just use 0 to get in skl_ddi_pll_get_freq()
1969 if (hw_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) in skl_ddi_pll_get_freq()
1970 return skl_ddi_wrpll_get_freq(i915, pll, dpll_hw_state); in skl_ddi_pll_get_freq()
1972 return skl_ddi_lcpll_get_freq(i915, pll, dpll_hw_state); in skl_ddi_pll_get_freq()
1978 i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref; in skl_update_dpll_ref_clks()
1984 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_dump_hw_state()
1987 hw_state->ctrl1, hw_state->cfgcr1, hw_state->cfgcr2); in skl_dump_hw_state()
1993 const struct skl_dpll_hw_state *a = &_a->skl; in skl_compare_hw_state()
1994 const struct skl_dpll_hw_state *b = &_b->skl; in skl_compare_hw_state()
1996 return a->ctrl1 == b->ctrl1 && in skl_compare_hw_state()
1997 a->cfgcr1 == b->cfgcr1 && in skl_compare_hw_state()
1998 a->cfgcr2 == b->cfgcr2; in skl_compare_hw_state()
2035 struct intel_shared_dpll *pll, in bxt_ddi_pll_enable() argument
2038 const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt; in bxt_ddi_pll_enable()
2039 enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */ in bxt_ddi_pll_enable()
2046 /* Non-SSC reference */ in bxt_ddi_pll_enable()
2055 drm_err(&i915->drm, in bxt_ddi_pll_enable()
2056 "Power state not set for PLL:%d\n", port); in bxt_ddi_pll_enable()
2065 PORT_PLL_P1_MASK | PORT_PLL_P2_MASK, hw_state->ebb0); in bxt_ddi_pll_enable()
2069 PORT_PLL_M2_INT_MASK, hw_state->pll0); in bxt_ddi_pll_enable()
2073 PORT_PLL_N_MASK, hw_state->pll1); in bxt_ddi_pll_enable()
2077 PORT_PLL_M2_FRAC_MASK, hw_state->pll2); in bxt_ddi_pll_enable()
2081 PORT_PLL_M2_FRAC_ENABLE, hw_state->pll3); in bxt_ddi_pll_enable()
2088 temp |= hw_state->pll6; in bxt_ddi_pll_enable()
2093 PORT_PLL_TARGET_CNT_MASK, hw_state->pll8); in bxt_ddi_pll_enable()
2096 PORT_PLL_LOCK_THRESHOLD_MASK, hw_state->pll9); in bxt_ddi_pll_enable()
2101 temp |= hw_state->pll10; in bxt_ddi_pll_enable()
2109 temp |= hw_state->ebb4; in bxt_ddi_pll_enable()
2112 /* Enable PLL */ in bxt_ddi_pll_enable()
2118 drm_err(&i915->drm, "PLL %d not locked\n", port); in bxt_ddi_pll_enable()
2133 temp |= hw_state->pcsdw12; in bxt_ddi_pll_enable()
2138 struct intel_shared_dpll *pll) in bxt_ddi_pll_disable() argument
2140 enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */ in bxt_ddi_pll_disable()
2151 drm_err(&i915->drm, in bxt_ddi_pll_disable()
2152 "Power state not reset for PLL:%d\n", port); in bxt_ddi_pll_disable()
2157 struct intel_shared_dpll *pll, in bxt_ddi_pll_get_hw_state() argument
2160 struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt; in bxt_ddi_pll_get_hw_state()
2161 enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */ in bxt_ddi_pll_get_hw_state()
2179 goto out; in bxt_ddi_pll_get_hw_state()
2181 hw_state->ebb0 = intel_de_read(i915, BXT_PORT_PLL_EBB_0(phy, ch)); in bxt_ddi_pll_get_hw_state()
2182 hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK; in bxt_ddi_pll_get_hw_state()
2184 hw_state->ebb4 = intel_de_read(i915, BXT_PORT_PLL_EBB_4(phy, ch)); in bxt_ddi_pll_get_hw_state()
2185 hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE; in bxt_ddi_pll_get_hw_state()
2187 hw_state->pll0 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 0)); in bxt_ddi_pll_get_hw_state()
2188 hw_state->pll0 &= PORT_PLL_M2_INT_MASK; in bxt_ddi_pll_get_hw_state()
2190 hw_state->pll1 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 1)); in bxt_ddi_pll_get_hw_state()
2191 hw_state->pll1 &= PORT_PLL_N_MASK; in bxt_ddi_pll_get_hw_state()
2193 hw_state->pll2 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 2)); in bxt_ddi_pll_get_hw_state()
2194 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK; in bxt_ddi_pll_get_hw_state()
2196 hw_state->pll3 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 3)); in bxt_ddi_pll_get_hw_state()
2197 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE; in bxt_ddi_pll_get_hw_state()
2199 hw_state->pll6 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 6)); in bxt_ddi_pll_get_hw_state()
2200 hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK | in bxt_ddi_pll_get_hw_state()
2204 hw_state->pll8 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 8)); in bxt_ddi_pll_get_hw_state()
2205 hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK; in bxt_ddi_pll_get_hw_state()
2207 hw_state->pll9 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 9)); in bxt_ddi_pll_get_hw_state()
2208 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK; in bxt_ddi_pll_get_hw_state()
2210 hw_state->pll10 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 10)); in bxt_ddi_pll_get_hw_state()
2211 hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H | in bxt_ddi_pll_get_hw_state()
2217 * here just read out lanes 0/1 and output a note if lanes 2/3 differ. in bxt_ddi_pll_get_hw_state()
2219 hw_state->pcsdw12 = intel_de_read(i915, in bxt_ddi_pll_get_hw_state()
2221 if (intel_de_read(i915, BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12) in bxt_ddi_pll_get_hw_state()
2222 drm_dbg(&i915->drm, in bxt_ddi_pll_get_hw_state()
2224 hw_state->pcsdw12, in bxt_ddi_pll_get_hw_state()
2227 hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD; in bxt_ddi_pll_get_hw_state()
2231 out: in bxt_ddi_pll_get_hw_state()
2237 /* pre-calculated values for DP linkrates */
2253 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in bxt_ddi_hdmi_pll_dividers()
2261 return -EINVAL; in bxt_ddi_hdmi_pll_dividers()
2263 drm_WARN_ON(&i915->drm, clk_div->m1 != 2); in bxt_ddi_hdmi_pll_dividers()
2271 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in bxt_ddi_dp_pll_dividers()
2276 if (crtc_state->port_clock == bxt_dp_clk_val[i].dot) { in bxt_ddi_dp_pll_dividers()
2282 chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, clk_div); in bxt_ddi_dp_pll_dividers()
2284 drm_WARN_ON(&i915->drm, clk_div->vco == 0 || in bxt_ddi_dp_pll_dividers()
2285 clk_div->dot != crtc_state->port_clock); in bxt_ddi_dp_pll_dividers()
2291 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in bxt_ddi_set_dpll_hw_state()
2292 struct bxt_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.bxt; in bxt_ddi_set_dpll_hw_state()
2293 int clock = crtc_state->port_clock; in bxt_ddi_set_dpll_hw_state()
2294 int vco = clk_div->vco; in bxt_ddi_set_dpll_hw_state()
2315 drm_err(&i915->drm, "Invalid VCO\n"); in bxt_ddi_set_dpll_hw_state()
2316 return -EINVAL; in bxt_ddi_set_dpll_hw_state()
2330 hw_state->ebb0 = PORT_PLL_P1(clk_div->p1) | PORT_PLL_P2(clk_div->p2); in bxt_ddi_set_dpll_hw_state()
2331 hw_state->pll0 = PORT_PLL_M2_INT(clk_div->m2 >> 22); in bxt_ddi_set_dpll_hw_state()
2332 hw_state->pll1 = PORT_PLL_N(clk_div->n); in bxt_ddi_set_dpll_hw_state()
2333 hw_state->pll2 = PORT_PLL_M2_FRAC(clk_div->m2 & 0x3fffff); in bxt_ddi_set_dpll_hw_state()
2335 if (clk_div->m2 & 0x3fffff) in bxt_ddi_set_dpll_hw_state()
2336 hw_state->pll3 = PORT_PLL_M2_FRAC_ENABLE; in bxt_ddi_set_dpll_hw_state()
2338 hw_state->pll6 = PORT_PLL_PROP_COEFF(prop_coef) | in bxt_ddi_set_dpll_hw_state()
2342 hw_state->pll8 = PORT_PLL_TARGET_CNT(targ_cnt); in bxt_ddi_set_dpll_hw_state()
2344 hw_state->pll9 = PORT_PLL_LOCK_THRESHOLD(5); in bxt_ddi_set_dpll_hw_state()
2346 hw_state->pll10 = PORT_PLL_DCO_AMP(15) | in bxt_ddi_set_dpll_hw_state()
2349 hw_state->ebb4 = PORT_PLL_10BIT_CLK_ENABLE; in bxt_ddi_set_dpll_hw_state()
2351 hw_state->pcsdw12 = LANESTAGGER_STRAP_OVRD | lanestagger; in bxt_ddi_set_dpll_hw_state()
2357 const struct intel_shared_dpll *pll, in bxt_ddi_pll_get_freq() argument
2360 const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt; in bxt_ddi_pll_get_freq()
2364 clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK, hw_state->pll0) << 22; in bxt_ddi_pll_get_freq()
2365 if (hw_state->pll3 & PORT_PLL_M2_FRAC_ENABLE) in bxt_ddi_pll_get_freq()
2367 hw_state->pll2); in bxt_ddi_pll_get_freq()
2368 clock.n = REG_FIELD_GET(PORT_PLL_N_MASK, hw_state->pll1); in bxt_ddi_pll_get_freq()
2369 clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK, hw_state->ebb0); in bxt_ddi_pll_get_freq()
2370 clock.p2 = REG_FIELD_GET(PORT_PLL_P2_MASK, hw_state->ebb0); in bxt_ddi_pll_get_freq()
2372 return chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, &clock); in bxt_ddi_pll_get_freq()
2388 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in bxt_ddi_hdmi_set_dpll_hw_state()
2398 crtc_state->port_clock = bxt_ddi_pll_get_freq(i915, NULL, in bxt_ddi_hdmi_set_dpll_hw_state()
2399 &crtc_state->dpll_hw_state); in bxt_ddi_hdmi_set_dpll_hw_state()
2416 return -EINVAL; in bxt_compute_dpll()
2425 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in bxt_get_dpll()
2426 struct intel_shared_dpll *pll; in bxt_get_dpll() local
2430 id = (enum intel_dpll_id) encoder->port; in bxt_get_dpll()
2431 pll = intel_get_shared_dpll_by_id(i915, id); in bxt_get_dpll()
2433 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] using pre-allocated %s\n", in bxt_get_dpll()
2434 crtc->base.base.id, crtc->base.name, pll->info->name); in bxt_get_dpll()
2437 pll, &crtc_state->dpll_hw_state); in bxt_get_dpll()
2439 crtc_state->shared_dpll = pll; in bxt_get_dpll()
2446 i915->display.dpll.ref_clks.ssc = 100000; in bxt_update_dpll_ref_clks()
2447 i915->display.dpll.ref_clks.nssc = 100000; in bxt_update_dpll_ref_clks()
2448 /* DSI non-SSC ref 19.2MHz */ in bxt_update_dpll_ref_clks()
2454 const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt; in bxt_dump_hw_state()
2459 hw_state->ebb0, hw_state->ebb4, in bxt_dump_hw_state()
2460 hw_state->pll0, hw_state->pll1, hw_state->pll2, hw_state->pll3, in bxt_dump_hw_state()
2461 hw_state->pll6, hw_state->pll8, hw_state->pll9, hw_state->pll10, in bxt_dump_hw_state()
2462 hw_state->pcsdw12); in bxt_dump_hw_state()
2468 const struct bxt_dpll_hw_state *a = &_a->bxt; in bxt_compare_hw_state()
2469 const struct bxt_dpll_hw_state *b = &_b->bxt; in bxt_compare_hw_state()
2471 return a->ebb0 == b->ebb0 && in bxt_compare_hw_state()
2472 a->ebb4 == b->ebb4 && in bxt_compare_hw_state()
2473 a->pll0 == b->pll0 && in bxt_compare_hw_state()
2474 a->pll1 == b->pll1 && in bxt_compare_hw_state()
2475 a->pll2 == b->pll2 && in bxt_compare_hw_state()
2476 a->pll3 == b->pll3 && in bxt_compare_hw_state()
2477 a->pll6 == b->pll6 && in bxt_compare_hw_state()
2478 a->pll8 == b->pll8 && in bxt_compare_hw_state()
2479 a->pll10 == b->pll10 && in bxt_compare_hw_state()
2480 a->pcsdw12 == b->pcsdw12; in bxt_compare_hw_state()
2491 { .name = "PORT PLL A", .funcs = &bxt_ddi_pll_funcs, .id = DPLL_ID_SKL_DPLL0, },
2492 { .name = "PORT PLL B", .funcs = &bxt_ddi_pll_funcs, .id = DPLL_ID_SKL_DPLL1, },
2493 { .name = "PORT PLL C", .funcs = &bxt_ddi_pll_funcs, .id = DPLL_ID_SKL_DPLL2, },
2554 params->kdiv = 1; in icl_wrpll_params_populate()
2557 params->kdiv = 2; in icl_wrpll_params_populate()
2560 params->kdiv = 4; in icl_wrpll_params_populate()
2568 params->pdiv = 1; in icl_wrpll_params_populate()
2571 params->pdiv = 2; in icl_wrpll_params_populate()
2574 params->pdiv = 4; in icl_wrpll_params_populate()
2577 params->pdiv = 8; in icl_wrpll_params_populate()
2585 params->qdiv_ratio = qdiv; in icl_wrpll_params_populate()
2586 params->qdiv_mode = (qdiv == 1) ? 0 : 1; in icl_wrpll_params_populate()
2590 params->dco_integer = dco >> 15; in icl_wrpll_params_populate()
2591 params->dco_fraction = dco & 0x7fff; in icl_wrpll_params_populate()
2595 * Display WA #22010492432: ehl, tgl, adl-s, adl-p
2604 i915->display.dpll.ref_clks.nssc == 38400; in ehl_combo_pll_div_frac_wa_needed()
2696 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in icl_calc_dp_combo_pll()
2698 i915->display.dpll.ref_clks.nssc == 24000 ? in icl_calc_dp_combo_pll()
2701 int clock = crtc_state->port_clock; in icl_calc_dp_combo_pll()
2712 return -EINVAL; in icl_calc_dp_combo_pll()
2718 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in icl_calc_tbt_pll()
2721 switch (i915->display.dpll.ref_clks.nssc) { in icl_calc_tbt_pll()
2723 MISSING_CASE(i915->display.dpll.ref_clks.nssc); in icl_calc_tbt_pll()
2734 switch (i915->display.dpll.ref_clks.nssc) { in icl_calc_tbt_pll()
2736 MISSING_CASE(i915->display.dpll.ref_clks.nssc); in icl_calc_tbt_pll()
2752 const struct intel_shared_dpll *pll, in icl_ddi_tbt_pll_get_freq() argument
2756 * The PLL outputs multiple frequencies at the same time, selection is in icl_ddi_tbt_pll_get_freq()
2759 drm_WARN_ON(&i915->drm, 1); in icl_ddi_tbt_pll_get_freq()
2766 int ref_clock = i915->display.dpll.ref_clks.nssc; in icl_wrpll_ref_clock()
2782 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in icl_calc_wrpll()
2784 u32 afe_clock = crtc_state->port_clock * 5; in icl_calc_wrpll()
2802 dco_centrality = abs(dco - dco_mid); in icl_calc_wrpll()
2813 return -EINVAL; in icl_calc_wrpll()
2823 const struct intel_shared_dpll *pll, in icl_ddi_combo_pll_get_freq() argument
2826 const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; in icl_ddi_combo_pll_get_freq()
2831 p0 = hw_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK; in icl_ddi_combo_pll_get_freq()
2832 p2 = hw_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK; in icl_ddi_combo_pll_get_freq()
2834 if (hw_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1)) in icl_ddi_combo_pll_get_freq()
2835 p1 = (hw_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >> in icl_ddi_combo_pll_get_freq()
2867 dco_freq = (hw_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * in icl_ddi_combo_pll_get_freq()
2870 dco_fraction = (hw_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >> in icl_ddi_combo_pll_get_freq()
2878 if (drm_WARN_ON(&i915->drm, p0 == 0 || p1 == 0 || p2 == 0)) in icl_ddi_combo_pll_get_freq()
2888 struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; in icl_calc_dpll_state()
2889 u32 dco_fraction = pll_params->dco_fraction; in icl_calc_dpll_state()
2894 hw_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(dco_fraction) | in icl_calc_dpll_state()
2895 pll_params->dco_integer; in icl_calc_dpll_state()
2897 hw_state->cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params->qdiv_ratio) | in icl_calc_dpll_state()
2898 DPLL_CFGCR1_QDIV_MODE(pll_params->qdiv_mode) | in icl_calc_dpll_state()
2899 DPLL_CFGCR1_KDIV(pll_params->kdiv) | in icl_calc_dpll_state()
2900 DPLL_CFGCR1_PDIV(pll_params->pdiv); in icl_calc_dpll_state()
2903 hw_state->cfgcr1 |= TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL; in icl_calc_dpll_state()
2905 hw_state->cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400; in icl_calc_dpll_state()
2907 if (i915->display.vbt.override_afc_startup) in icl_calc_dpll_state()
2908 hw_state->div0 = TGL_DPLL0_DIV0_AFC_STARTUP(i915->display.vbt.override_afc_startup_val); in icl_calc_dpll_state()
2927 for (div2 = 10; div2 > 0; div2--) { in icl_mg_pll_find_divisors()
2939 * working on HW for DP alt-mode at least in icl_mg_pll_find_divisors()
2969 hw_state->mg_refclkin_ctl = MG_REFCLKIN_CTL_OD_2_MUX(1); in icl_mg_pll_find_divisors()
2971 hw_state->mg_clktop2_coreclkctl1 = in icl_mg_pll_find_divisors()
2974 hw_state->mg_clktop2_hsclkctl = in icl_mg_pll_find_divisors()
2984 return -EINVAL; in icl_mg_pll_find_divisors()
2989 * adapted to integer-only calculation, that's why it looks so different.
2994 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in icl_calc_mg_pll_state()
2995 struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; in icl_calc_mg_pll_state()
2996 int refclk_khz = i915->display.dpll.ref_clks.nssc; in icl_calc_mg_pll_state()
2997 int clock = crtc_state->port_clock; in icl_calc_mg_pll_state()
3023 return -EINVAL; in icl_calc_mg_pll_state()
3049 return -EINVAL; in icl_calc_mg_pll_state()
3100 hw_state->mg_pll_div0 = DKL_PLL_DIV0_INTEG_COEFF(int_coeff) | in icl_calc_mg_pll_state()
3104 if (i915->display.vbt.override_afc_startup) { in icl_calc_mg_pll_state()
3105 u8 val = i915->display.vbt.override_afc_startup_val; in icl_calc_mg_pll_state()
3107 hw_state->mg_pll_div0 |= DKL_PLL_DIV0_AFC_STARTUP(val); in icl_calc_mg_pll_state()
3110 hw_state->mg_pll_div1 = DKL_PLL_DIV1_IREF_TRIM(iref_trim) | in icl_calc_mg_pll_state()
3113 hw_state->mg_pll_ssc = DKL_PLL_SSC_IREF_NDIV_RATIO(iref_ndiv) | in icl_calc_mg_pll_state()
3118 hw_state->mg_pll_bias = (m2div_frac ? DKL_PLL_BIAS_FRAC_EN_H : 0) | in icl_calc_mg_pll_state()
3121 hw_state->mg_pll_tdc_coldst_bias = in icl_calc_mg_pll_state()
3126 hw_state->mg_pll_div0 = in icl_calc_mg_pll_state()
3131 hw_state->mg_pll_div1 = in icl_calc_mg_pll_state()
3137 hw_state->mg_pll_lf = in icl_calc_mg_pll_state()
3144 hw_state->mg_pll_frac_lock = in icl_calc_mg_pll_state()
3151 hw_state->mg_pll_frac_lock |= in icl_calc_mg_pll_state()
3154 hw_state->mg_pll_ssc = in icl_calc_mg_pll_state()
3162 hw_state->mg_pll_tdc_coldst_bias = in icl_calc_mg_pll_state()
3169 hw_state->mg_pll_bias = in icl_calc_mg_pll_state()
3179 hw_state->mg_pll_tdc_coldst_bias_mask = in icl_calc_mg_pll_state()
3181 hw_state->mg_pll_bias_mask = 0; in icl_calc_mg_pll_state()
3183 hw_state->mg_pll_tdc_coldst_bias_mask = -1U; in icl_calc_mg_pll_state()
3184 hw_state->mg_pll_bias_mask = -1U; in icl_calc_mg_pll_state()
3187 hw_state->mg_pll_tdc_coldst_bias &= in icl_calc_mg_pll_state()
3188 hw_state->mg_pll_tdc_coldst_bias_mask; in icl_calc_mg_pll_state()
3189 hw_state->mg_pll_bias &= hw_state->mg_pll_bias_mask; in icl_calc_mg_pll_state()
3196 const struct intel_shared_dpll *pll, in icl_ddi_mg_pll_get_freq() argument
3199 const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; in icl_ddi_mg_pll_get_freq()
3203 ref_clock = i915->display.dpll.ref_clks.nssc; in icl_ddi_mg_pll_get_freq()
3206 m1 = hw_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK; in icl_ddi_mg_pll_get_freq()
3208 m2_int = hw_state->mg_pll_div0 & DKL_PLL_DIV0_FBDIV_INT_MASK; in icl_ddi_mg_pll_get_freq()
3210 if (hw_state->mg_pll_bias & DKL_PLL_BIAS_FRAC_EN_H) { in icl_ddi_mg_pll_get_freq()
3211 m2_frac = hw_state->mg_pll_bias & in icl_ddi_mg_pll_get_freq()
3218 m1 = hw_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK; in icl_ddi_mg_pll_get_freq()
3219 m2_int = hw_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK; in icl_ddi_mg_pll_get_freq()
3221 if (hw_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) { in icl_ddi_mg_pll_get_freq()
3222 m2_frac = hw_state->mg_pll_div0 & in icl_ddi_mg_pll_get_freq()
3230 switch (hw_state->mg_clktop2_hsclkctl & in icl_ddi_mg_pll_get_freq()
3245 MISSING_CASE(hw_state->mg_clktop2_hsclkctl); in icl_ddi_mg_pll_get_freq()
3249 div2 = (hw_state->mg_clktop2_hsclkctl & in icl_ddi_mg_pll_get_freq()
3269 * icl_set_active_port_dpll - select the active port DPLL for a given CRTC
3280 &crtc_state->icl_port_dplls[port_dpll_id]; in icl_set_active_port_dpll()
3282 crtc_state->shared_dpll = port_dpll->pll; in icl_set_active_port_dpll()
3283 crtc_state->dpll_hw_state = port_dpll->hw_state; in icl_set_active_port_dpll()
3295 primary_port = encoder->type == INTEL_OUTPUT_DP_MST ? in icl_update_active_dpll()
3296 enc_to_mst(encoder)->primary : in icl_update_active_dpll()
3310 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in icl_compute_combo_phy_dpll()
3314 &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_compute_combo_phy_dpll()
3327 icl_calc_dpll_state(i915, &pll_params, &port_dpll->hw_state); in icl_compute_combo_phy_dpll()
3332 crtc_state->port_clock = icl_ddi_combo_pll_get_freq(i915, NULL, in icl_compute_combo_phy_dpll()
3333 &port_dpll->hw_state); in icl_compute_combo_phy_dpll()
3343 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in icl_get_combo_phy_dpll()
3347 &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_get_combo_phy_dpll()
3348 enum port port = encoder->port; in icl_get_combo_phy_dpll()
3385 port_dpll->pll = intel_find_shared_dpll(state, crtc, in icl_get_combo_phy_dpll()
3386 &port_dpll->hw_state, in icl_get_combo_phy_dpll()
3388 if (!port_dpll->pll) in icl_get_combo_phy_dpll()
3389 return -EINVAL; in icl_get_combo_phy_dpll()
3392 port_dpll->pll, &port_dpll->hw_state); in icl_get_combo_phy_dpll()
3402 struct drm_i915_private *i915 = to_i915(state->base.dev); in icl_compute_tc_phy_dplls()
3408 &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_compute_tc_phy_dplls()
3412 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_compute_tc_phy_dplls()
3417 icl_calc_dpll_state(i915, &pll_params, &port_dpll->hw_state); in icl_compute_tc_phy_dplls()
3419 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY]; in icl_compute_tc_phy_dplls()
3420 ret = icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state); in icl_compute_tc_phy_dplls()
3425 if (old_crtc_state->shared_dpll && in icl_compute_tc_phy_dplls()
3426 old_crtc_state->shared_dpll->info->id == DPLL_ID_ICL_TBTPLL) in icl_compute_tc_phy_dplls()
3431 crtc_state->port_clock = icl_ddi_mg_pll_get_freq(i915, NULL, in icl_compute_tc_phy_dplls()
3432 &port_dpll->hw_state); in icl_compute_tc_phy_dplls()
3444 &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_get_tc_phy_dplls()
3448 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_get_tc_phy_dplls()
3449 port_dpll->pll = intel_find_shared_dpll(state, crtc, in icl_get_tc_phy_dplls()
3450 &port_dpll->hw_state, in icl_get_tc_phy_dplls()
3452 if (!port_dpll->pll) in icl_get_tc_phy_dplls()
3453 return -EINVAL; in icl_get_tc_phy_dplls()
3455 port_dpll->pll, &port_dpll->hw_state); in icl_get_tc_phy_dplls()
3458 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY]; in icl_get_tc_phy_dplls()
3460 port_dpll->pll = intel_find_shared_dpll(state, crtc, in icl_get_tc_phy_dplls()
3461 &port_dpll->hw_state, in icl_get_tc_phy_dplls()
3463 if (!port_dpll->pll) { in icl_get_tc_phy_dplls()
3464 ret = -EINVAL; in icl_get_tc_phy_dplls()
3468 port_dpll->pll, &port_dpll->hw_state); in icl_get_tc_phy_dplls()
3475 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_get_tc_phy_dplls()
3476 intel_unreference_shared_dpll(state, crtc, port_dpll->pll); in icl_get_tc_phy_dplls()
3490 MISSING_CASE(encoder->port); in icl_compute_dplls()
3504 MISSING_CASE(encoder->port); in icl_get_dplls()
3506 return -EINVAL; in icl_get_dplls()
3518 new_crtc_state->shared_dpll = NULL; in icl_put_dplls()
3522 &old_crtc_state->icl_port_dplls[id]; in icl_put_dplls()
3524 &new_crtc_state->icl_port_dplls[id]; in icl_put_dplls()
3526 new_port_dpll->pll = NULL; in icl_put_dplls()
3528 if (!old_port_dpll->pll) in icl_put_dplls()
3531 intel_unreference_shared_dpll(state, crtc, old_port_dpll->pll); in icl_put_dplls()
3536 struct intel_shared_dpll *pll, in mg_pll_get_hw_state() argument
3539 struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; in mg_pll_get_hw_state()
3540 const enum intel_dpll_id id = pll->info->id; in mg_pll_get_hw_state()
3546 i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll); in mg_pll_get_hw_state()
3555 goto out; in mg_pll_get_hw_state()
3557 hw_state->mg_refclkin_ctl = intel_de_read(i915, in mg_pll_get_hw_state()
3559 hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK; in mg_pll_get_hw_state()
3561 hw_state->mg_clktop2_coreclkctl1 = in mg_pll_get_hw_state()
3563 hw_state->mg_clktop2_coreclkctl1 &= in mg_pll_get_hw_state()
3566 hw_state->mg_clktop2_hsclkctl = in mg_pll_get_hw_state()
3568 hw_state->mg_clktop2_hsclkctl &= in mg_pll_get_hw_state()
3574 hw_state->mg_pll_div0 = intel_de_read(i915, MG_PLL_DIV0(tc_port)); in mg_pll_get_hw_state()
3575 hw_state->mg_pll_div1 = intel_de_read(i915, MG_PLL_DIV1(tc_port)); in mg_pll_get_hw_state()
3576 hw_state->mg_pll_lf = intel_de_read(i915, MG_PLL_LF(tc_port)); in mg_pll_get_hw_state()
3577 hw_state->mg_pll_frac_lock = intel_de_read(i915, in mg_pll_get_hw_state()
3579 hw_state->mg_pll_ssc = intel_de_read(i915, MG_PLL_SSC(tc_port)); in mg_pll_get_hw_state()
3581 hw_state->mg_pll_bias = intel_de_read(i915, MG_PLL_BIAS(tc_port)); in mg_pll_get_hw_state()
3582 hw_state->mg_pll_tdc_coldst_bias = in mg_pll_get_hw_state()
3585 if (i915->display.dpll.ref_clks.nssc == 38400) { in mg_pll_get_hw_state()
3586 hw_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART; in mg_pll_get_hw_state()
3587 hw_state->mg_pll_bias_mask = 0; in mg_pll_get_hw_state()
3589 hw_state->mg_pll_tdc_coldst_bias_mask = -1U; in mg_pll_get_hw_state()
3590 hw_state->mg_pll_bias_mask = -1U; in mg_pll_get_hw_state()
3593 hw_state->mg_pll_tdc_coldst_bias &= hw_state->mg_pll_tdc_coldst_bias_mask; in mg_pll_get_hw_state()
3594 hw_state->mg_pll_bias &= hw_state->mg_pll_bias_mask; in mg_pll_get_hw_state()
3597 out: in mg_pll_get_hw_state()
3603 struct intel_shared_dpll *pll, in dkl_pll_get_hw_state() argument
3606 struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; in dkl_pll_get_hw_state()
3607 const enum intel_dpll_id id = pll->info->id; in dkl_pll_get_hw_state()
3618 val = intel_de_read(i915, intel_tc_pll_enable_reg(i915, pll)); in dkl_pll_get_hw_state()
3620 goto out; in dkl_pll_get_hw_state()
3626 hw_state->mg_refclkin_ctl = intel_dkl_phy_read(i915, in dkl_pll_get_hw_state()
3628 hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK; in dkl_pll_get_hw_state()
3630 hw_state->mg_clktop2_hsclkctl = in dkl_pll_get_hw_state()
3632 hw_state->mg_clktop2_hsclkctl &= in dkl_pll_get_hw_state()
3638 hw_state->mg_clktop2_coreclkctl1 = in dkl_pll_get_hw_state()
3640 hw_state->mg_clktop2_coreclkctl1 &= in dkl_pll_get_hw_state()
3643 hw_state->mg_pll_div0 = intel_dkl_phy_read(i915, DKL_PLL_DIV0(tc_port)); in dkl_pll_get_hw_state()
3645 if (i915->display.vbt.override_afc_startup) in dkl_pll_get_hw_state()
3647 hw_state->mg_pll_div0 &= val; in dkl_pll_get_hw_state()
3649 hw_state->mg_pll_div1 = intel_dkl_phy_read(i915, DKL_PLL_DIV1(tc_port)); in dkl_pll_get_hw_state()
3650 hw_state->mg_pll_div1 &= (DKL_PLL_DIV1_IREF_TRIM_MASK | in dkl_pll_get_hw_state()
3653 hw_state->mg_pll_ssc = intel_dkl_phy_read(i915, DKL_PLL_SSC(tc_port)); in dkl_pll_get_hw_state()
3654 hw_state->mg_pll_ssc &= (DKL_PLL_SSC_IREF_NDIV_RATIO_MASK | in dkl_pll_get_hw_state()
3659 hw_state->mg_pll_bias = intel_dkl_phy_read(i915, DKL_PLL_BIAS(tc_port)); in dkl_pll_get_hw_state()
3660 hw_state->mg_pll_bias &= (DKL_PLL_BIAS_FRAC_EN_H | in dkl_pll_get_hw_state()
3663 hw_state->mg_pll_tdc_coldst_bias = in dkl_pll_get_hw_state()
3665 hw_state->mg_pll_tdc_coldst_bias &= (DKL_PLL_TDC_SSC_STEP_SIZE_MASK | in dkl_pll_get_hw_state()
3669 out: in dkl_pll_get_hw_state()
3675 struct intel_shared_dpll *pll, in icl_pll_get_hw_state() argument
3679 struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; in icl_pll_get_hw_state()
3680 const enum intel_dpll_id id = pll->info->id; in icl_pll_get_hw_state()
3692 goto out; in icl_pll_get_hw_state()
3695 hw_state->cfgcr0 = intel_de_read(i915, ADLS_DPLL_CFGCR0(id)); in icl_pll_get_hw_state()
3696 hw_state->cfgcr1 = intel_de_read(i915, ADLS_DPLL_CFGCR1(id)); in icl_pll_get_hw_state()
3698 hw_state->cfgcr0 = intel_de_read(i915, DG1_DPLL_CFGCR0(id)); in icl_pll_get_hw_state()
3699 hw_state->cfgcr1 = intel_de_read(i915, DG1_DPLL_CFGCR1(id)); in icl_pll_get_hw_state()
3701 hw_state->cfgcr0 = intel_de_read(i915, in icl_pll_get_hw_state()
3703 hw_state->cfgcr1 = intel_de_read(i915, in icl_pll_get_hw_state()
3706 hw_state->cfgcr0 = intel_de_read(i915, in icl_pll_get_hw_state()
3708 hw_state->cfgcr1 = intel_de_read(i915, in icl_pll_get_hw_state()
3710 if (i915->display.vbt.override_afc_startup) { in icl_pll_get_hw_state()
3711 hw_state->div0 = intel_de_read(i915, TGL_DPLL0_DIV0(id)); in icl_pll_get_hw_state()
3712 hw_state->div0 &= TGL_DPLL0_DIV0_AFC_STARTUP_MASK; in icl_pll_get_hw_state()
3717 hw_state->cfgcr0 = intel_de_read(i915, in icl_pll_get_hw_state()
3719 hw_state->cfgcr1 = intel_de_read(i915, in icl_pll_get_hw_state()
3722 hw_state->cfgcr0 = intel_de_read(i915, in icl_pll_get_hw_state()
3724 hw_state->cfgcr1 = intel_de_read(i915, in icl_pll_get_hw_state()
3730 out: in icl_pll_get_hw_state()
3736 struct intel_shared_dpll *pll, in combo_pll_get_hw_state() argument
3739 i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll); in combo_pll_get_hw_state()
3741 return icl_pll_get_hw_state(i915, pll, dpll_hw_state, enable_reg); in combo_pll_get_hw_state()
3745 struct intel_shared_dpll *pll, in tbt_pll_get_hw_state() argument
3748 return icl_pll_get_hw_state(i915, pll, dpll_hw_state, TBT_PLL_ENABLE); in tbt_pll_get_hw_state()
3752 struct intel_shared_dpll *pll, in icl_dpll_write() argument
3755 const enum intel_dpll_id id = pll->info->id; in icl_dpll_write()
3782 intel_de_write(i915, cfgcr0_reg, hw_state->cfgcr0); in icl_dpll_write()
3783 intel_de_write(i915, cfgcr1_reg, hw_state->cfgcr1); in icl_dpll_write()
3784 drm_WARN_ON_ONCE(&i915->drm, i915->display.vbt.override_afc_startup && in icl_dpll_write()
3786 if (i915->display.vbt.override_afc_startup && in icl_dpll_write()
3789 TGL_DPLL0_DIV0_AFC_STARTUP_MASK, hw_state->div0); in icl_dpll_write()
3794 struct intel_shared_dpll *pll, in icl_mg_pll_write() argument
3797 enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id); in icl_mg_pll_write()
3806 MG_REFCLKIN_CTL_OD_2_MUX_MASK, hw_state->mg_refclkin_ctl); in icl_mg_pll_write()
3810 hw_state->mg_clktop2_coreclkctl1); in icl_mg_pll_write()
3817 hw_state->mg_clktop2_hsclkctl); in icl_mg_pll_write()
3819 intel_de_write(i915, MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0); in icl_mg_pll_write()
3820 intel_de_write(i915, MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1); in icl_mg_pll_write()
3821 intel_de_write(i915, MG_PLL_LF(tc_port), hw_state->mg_pll_lf); in icl_mg_pll_write()
3823 hw_state->mg_pll_frac_lock); in icl_mg_pll_write()
3824 intel_de_write(i915, MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc); in icl_mg_pll_write()
3827 hw_state->mg_pll_bias_mask, hw_state->mg_pll_bias); in icl_mg_pll_write()
3830 hw_state->mg_pll_tdc_coldst_bias_mask, in icl_mg_pll_write()
3831 hw_state->mg_pll_tdc_coldst_bias); in icl_mg_pll_write()
3837 struct intel_shared_dpll *pll, in dkl_pll_write() argument
3840 enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id); in dkl_pll_write()
3850 val |= hw_state->mg_refclkin_ctl; in dkl_pll_write()
3855 val |= hw_state->mg_clktop2_coreclkctl1; in dkl_pll_write()
3863 val |= hw_state->mg_clktop2_hsclkctl; in dkl_pll_write()
3867 if (i915->display.vbt.override_afc_startup) in dkl_pll_write()
3870 hw_state->mg_pll_div0); in dkl_pll_write()
3875 val |= hw_state->mg_pll_div1; in dkl_pll_write()
3883 val |= hw_state->mg_pll_ssc; in dkl_pll_write()
3889 val |= hw_state->mg_pll_bias; in dkl_pll_write()
3895 val |= hw_state->mg_pll_tdc_coldst_bias; in dkl_pll_write()
3902 struct intel_shared_dpll *pll, in icl_pll_power_enable() argument
3912 drm_err(&i915->drm, "PLL %d Power not enabled\n", in icl_pll_power_enable()
3913 pll->info->id); in icl_pll_power_enable()
3917 struct intel_shared_dpll *pll, in icl_pll_enable() argument
3924 drm_err(&i915->drm, "PLL %d not locked\n", pll->info->id); in icl_pll_enable()
3927 static void adlp_cmtg_clock_gating_wa(struct drm_i915_private *i915, struct intel_shared_dpll *pll) in adlp_cmtg_clock_gating_wa() argument
3932 pll->info->id != DPLL_ID_ICL_DPLL0) in adlp_cmtg_clock_gating_wa()
3935 * Wa_16011069516:adl-p[a0] in adlp_cmtg_clock_gating_wa()
3947 if (drm_WARN_ON(&i915->drm, val & ~DISABLE_DPT_CLK_GATING)) in adlp_cmtg_clock_gating_wa()
3948 drm_dbg_kms(&i915->drm, "Unexpected flags in TRANS_CMTG_CHICKEN: %08x\n", val); in adlp_cmtg_clock_gating_wa()
3952 struct intel_shared_dpll *pll, in combo_pll_enable() argument
3955 const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; in combo_pll_enable()
3956 i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll); in combo_pll_enable()
3958 icl_pll_power_enable(i915, pll, enable_reg); in combo_pll_enable()
3960 icl_dpll_write(i915, pll, hw_state); in combo_pll_enable()
3968 icl_pll_enable(i915, pll, enable_reg); in combo_pll_enable()
3970 adlp_cmtg_clock_gating_wa(i915, pll); in combo_pll_enable()
3976 struct intel_shared_dpll *pll, in tbt_pll_enable() argument
3979 const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; in tbt_pll_enable()
3981 icl_pll_power_enable(i915, pll, TBT_PLL_ENABLE); in tbt_pll_enable()
3983 icl_dpll_write(i915, pll, hw_state); in tbt_pll_enable()
3991 icl_pll_enable(i915, pll, TBT_PLL_ENABLE); in tbt_pll_enable()
3997 struct intel_shared_dpll *pll, in mg_pll_enable() argument
4000 const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; in mg_pll_enable()
4001 i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll); in mg_pll_enable()
4003 icl_pll_power_enable(i915, pll, enable_reg); in mg_pll_enable()
4006 dkl_pll_write(i915, pll, hw_state); in mg_pll_enable()
4008 icl_mg_pll_write(i915, pll, hw_state); in mg_pll_enable()
4016 icl_pll_enable(i915, pll, enable_reg); in mg_pll_enable()
4022 struct intel_shared_dpll *pll, in icl_pll_disable() argument
4037 drm_err(&i915->drm, "PLL %d locked\n", pll->info->id); in icl_pll_disable()
4048 drm_err(&i915->drm, "PLL %d Power not disabled\n", in icl_pll_disable()
4049 pll->info->id); in icl_pll_disable()
4053 struct intel_shared_dpll *pll) in combo_pll_disable() argument
4055 i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll); in combo_pll_disable()
4057 icl_pll_disable(i915, pll, enable_reg); in combo_pll_disable()
4061 struct intel_shared_dpll *pll) in tbt_pll_disable() argument
4063 icl_pll_disable(i915, pll, TBT_PLL_ENABLE); in tbt_pll_disable()
4067 struct intel_shared_dpll *pll) in mg_pll_disable() argument
4069 i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll); in mg_pll_disable()
4071 icl_pll_disable(i915, pll, enable_reg); in mg_pll_disable()
4077 i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref; in icl_update_dpll_ref_clks()
4083 const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; in icl_dump_hw_state()
4091 hw_state->cfgcr0, hw_state->cfgcr1, hw_state->div0, in icl_dump_hw_state()
4092 hw_state->mg_refclkin_ctl, in icl_dump_hw_state()
4093 hw_state->mg_clktop2_coreclkctl1, in icl_dump_hw_state()
4094 hw_state->mg_clktop2_hsclkctl, in icl_dump_hw_state()
4095 hw_state->mg_pll_div0, in icl_dump_hw_state()
4096 hw_state->mg_pll_div1, in icl_dump_hw_state()
4097 hw_state->mg_pll_lf, in icl_dump_hw_state()
4098 hw_state->mg_pll_frac_lock, in icl_dump_hw_state()
4099 hw_state->mg_pll_ssc, in icl_dump_hw_state()
4100 hw_state->mg_pll_bias, in icl_dump_hw_state()
4101 hw_state->mg_pll_tdc_coldst_bias); in icl_dump_hw_state()
4107 const struct icl_dpll_hw_state *a = &_a->icl; in icl_compare_hw_state()
4108 const struct icl_dpll_hw_state *b = &_b->icl; in icl_compare_hw_state()
4111 return a->cfgcr0 == b->cfgcr0 && in icl_compare_hw_state()
4112 a->cfgcr1 == b->cfgcr1 && in icl_compare_hw_state()
4113 a->div0 == b->div0 && in icl_compare_hw_state()
4114 a->mg_refclkin_ctl == b->mg_refclkin_ctl && in icl_compare_hw_state()
4115 a->mg_clktop2_coreclkctl1 == b->mg_clktop2_coreclkctl1 && in icl_compare_hw_state()
4116 a->mg_clktop2_hsclkctl == b->mg_clktop2_hsclkctl && in icl_compare_hw_state()
4117 a->mg_pll_div0 == b->mg_pll_div0 && in icl_compare_hw_state()
4118 a->mg_pll_div1 == b->mg_pll_div1 && in icl_compare_hw_state()
4119 a->mg_pll_lf == b->mg_pll_lf && in icl_compare_hw_state()
4120 a->mg_pll_frac_lock == b->mg_pll_frac_lock && in icl_compare_hw_state()
4121 a->mg_pll_ssc == b->mg_pll_ssc && in icl_compare_hw_state()
4122 a->mg_pll_bias == b->mg_pll_bias && in icl_compare_hw_state()
4123 a->mg_pll_tdc_coldst_bias == b->mg_pll_tdc_coldst_bias; in icl_compare_hw_state()
4150 { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
4152 { .name = "MG PLL 1", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
4153 { .name = "MG PLL 2", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
4154 { .name = "MG PLL 3", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
4155 { .name = "MG PLL 4", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },
4198 { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
4200 { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
4201 { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
4202 { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
4203 { .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },
4204 { .name = "TC PLL 5", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL5, },
4205 { .name = "TC PLL 6", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL6, },
4276 { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
4278 { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
4279 { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
4280 { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
4281 { .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },
4297 * intel_shared_dpll_init - Initialize shared DPLLs
4308 mutex_init(&i915->display.dpll.lock); in intel_shared_dpll_init()
4339 dpll_info = dpll_mgr->dpll_info; in intel_shared_dpll_init()
4342 if (drm_WARN_ON(&i915->drm, in intel_shared_dpll_init()
4343 i >= ARRAY_SIZE(i915->display.dpll.shared_dplls))) in intel_shared_dpll_init()
4347 if (drm_WARN_ON(&i915->drm, dpll_info[i].id >= 32)) in intel_shared_dpll_init()
4350 i915->display.dpll.shared_dplls[i].info = &dpll_info[i]; in intel_shared_dpll_init()
4351 i915->display.dpll.shared_dplls[i].index = i; in intel_shared_dpll_init()
4354 i915->display.dpll.mgr = dpll_mgr; in intel_shared_dpll_init()
4355 i915->display.dpll.num_shared_dpll = i; in intel_shared_dpll_init()
4359 * intel_compute_shared_dplls - compute DPLL state CRTC and encoder combination
4376 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_compute_shared_dplls()
4377 const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr; in intel_compute_shared_dplls()
4379 if (drm_WARN_ON(&i915->drm, !dpll_mgr)) in intel_compute_shared_dplls()
4380 return -EINVAL; in intel_compute_shared_dplls()
4382 return dpll_mgr->compute_dplls(state, crtc, encoder); in intel_compute_shared_dplls()
4386 * intel_reserve_shared_dplls - reserve DPLLs for CRTC and encoder combination
4409 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_reserve_shared_dplls()
4410 const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr; in intel_reserve_shared_dplls()
4412 if (drm_WARN_ON(&i915->drm, !dpll_mgr)) in intel_reserve_shared_dplls()
4413 return -EINVAL; in intel_reserve_shared_dplls()
4415 return dpll_mgr->get_dplls(state, crtc, encoder); in intel_reserve_shared_dplls()
4419 * intel_release_shared_dplls - end use of DPLLs by CRTC in atomic state
4432 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_release_shared_dplls()
4433 const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr; in intel_release_shared_dplls()
4444 dpll_mgr->put_dplls(state, crtc); in intel_release_shared_dplls()
4448 * intel_update_active_dpll - update the active DPLL for a CRTC/encoder
4461 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_update_active_dpll()
4462 const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr; in intel_update_active_dpll()
4464 if (drm_WARN_ON(&i915->drm, !dpll_mgr)) in intel_update_active_dpll()
4467 dpll_mgr->update_active_dpll(state, crtc, encoder); in intel_update_active_dpll()
4471 * intel_dpll_get_freq - calculate the DPLL's output frequency
4473 * @pll: DPLL for which to calculate the output frequency
4476 * Return the output frequency corresponding to @pll's passed in @dpll_hw_state.
4479 const struct intel_shared_dpll *pll, in intel_dpll_get_freq() argument
4482 if (drm_WARN_ON(&i915->drm, !pll->info->funcs->get_freq)) in intel_dpll_get_freq()
4485 return pll->info->funcs->get_freq(i915, pll, dpll_hw_state); in intel_dpll_get_freq()
4489 * intel_dpll_get_hw_state - readout the DPLL's hardware state
4491 * @pll: DPLL for which to calculate the output frequency
4494 * Read out @pll's hardware state into @dpll_hw_state.
4497 struct intel_shared_dpll *pll, in intel_dpll_get_hw_state() argument
4500 return pll->info->funcs->get_hw_state(i915, pll, dpll_hw_state); in intel_dpll_get_hw_state()
4504 struct intel_shared_dpll *pll) in readout_dpll_hw_state() argument
4508 pll->on = intel_dpll_get_hw_state(i915, pll, &pll->state.hw_state); in readout_dpll_hw_state()
4510 if (pll->on && pll->info->power_domain) in readout_dpll_hw_state()
4511 pll->wakeref = intel_display_power_get(i915, pll->info->power_domain); in readout_dpll_hw_state()
4513 pll->state.pipe_mask = 0; in readout_dpll_hw_state()
4514 for_each_intel_crtc(&i915->drm, crtc) { in readout_dpll_hw_state()
4516 to_intel_crtc_state(crtc->base.state); in readout_dpll_hw_state()
4518 if (crtc_state->hw.active && crtc_state->shared_dpll == pll) in readout_dpll_hw_state()
4519 intel_reference_shared_dpll_crtc(crtc, pll, &pll->state); in readout_dpll_hw_state()
4521 pll->active_mask = pll->state.pipe_mask; in readout_dpll_hw_state()
4523 drm_dbg_kms(&i915->drm, in readout_dpll_hw_state()
4525 pll->info->name, pll->state.pipe_mask, pll->on); in readout_dpll_hw_state()
4530 if (i915->display.dpll.mgr && i915->display.dpll.mgr->update_ref_clks) in intel_dpll_update_ref_clks()
4531 i915->display.dpll.mgr->update_ref_clks(i915); in intel_dpll_update_ref_clks()
4536 struct intel_shared_dpll *pll; in intel_dpll_readout_hw_state() local
4539 for_each_shared_dpll(i915, pll, i) in intel_dpll_readout_hw_state()
4540 readout_dpll_hw_state(i915, pll); in intel_dpll_readout_hw_state()
4544 struct intel_shared_dpll *pll) in sanitize_dpll_state() argument
4546 if (!pll->on) in sanitize_dpll_state()
4549 adlp_cmtg_clock_gating_wa(i915, pll); in sanitize_dpll_state()
4551 if (pll->active_mask) in sanitize_dpll_state()
4554 drm_dbg_kms(&i915->drm, in sanitize_dpll_state()
4556 pll->info->name); in sanitize_dpll_state()
4558 _intel_disable_shared_dpll(i915, pll); in sanitize_dpll_state()
4563 struct intel_shared_dpll *pll; in intel_dpll_sanitize_state() local
4566 for_each_shared_dpll(i915, pll, i) in intel_dpll_sanitize_state()
4567 sanitize_dpll_state(i915, pll); in intel_dpll_sanitize_state()
4571 * intel_dpll_dump_hw_state - dump hw_state
4576 * Dumo out the relevant values in @dpll_hw_state.
4582 if (i915->display.dpll.mgr) { in intel_dpll_dump_hw_state()
4583 i915->display.dpll.mgr->dump_hw_state(p, dpll_hw_state); in intel_dpll_dump_hw_state()
4593 * intel_dpll_compare_hw_state - compare the two states
4606 if (i915->display.dpll.mgr) { in intel_dpll_compare_hw_state()
4607 return i915->display.dpll.mgr->compare_hw_state(a, b); in intel_dpll_compare_hw_state()
4618 struct intel_shared_dpll *pll, in verify_single_dpll_state() argument
4626 active = intel_dpll_get_hw_state(i915, pll, &dpll_hw_state); in verify_single_dpll_state()
4628 if (!pll->info->always_on) { in verify_single_dpll_state()
4629 I915_STATE_WARN(i915, !pll->on && pll->active_mask, in verify_single_dpll_state()
4630 "%s: pll in active use but not on in sw tracking\n", in verify_single_dpll_state()
4631 pll->info->name); in verify_single_dpll_state()
4632 I915_STATE_WARN(i915, pll->on && !pll->active_mask, in verify_single_dpll_state()
4633 "%s: pll is on but not used by any active pipe\n", in verify_single_dpll_state()
4634 pll->info->name); in verify_single_dpll_state()
4635 I915_STATE_WARN(i915, pll->on != active, in verify_single_dpll_state()
4636 "%s: pll on state mismatch (expected %i, found %i)\n", in verify_single_dpll_state()
4637 pll->info->name, pll->on, active); in verify_single_dpll_state()
4642 pll->active_mask & ~pll->state.pipe_mask, in verify_single_dpll_state()
4643 "%s: more active pll users than references: 0x%x vs 0x%x\n", in verify_single_dpll_state()
4644 pll->info->name, pll->active_mask, pll->state.pipe_mask); in verify_single_dpll_state()
4649 pipe_mask = BIT(crtc->pipe); in verify_single_dpll_state()
4651 if (new_crtc_state->hw.active) in verify_single_dpll_state()
4652 I915_STATE_WARN(i915, !(pll->active_mask & pipe_mask), in verify_single_dpll_state()
4653 "%s: pll active mismatch (expected pipe %c in active mask 0x%x)\n", in verify_single_dpll_state()
4654 pll->info->name, pipe_name(crtc->pipe), pll->active_mask); in verify_single_dpll_state()
4656 I915_STATE_WARN(i915, pll->active_mask & pipe_mask, in verify_single_dpll_state()
4657 "%s: pll active mismatch (didn't expect pipe %c in active mask 0x%x)\n", in verify_single_dpll_state()
4658 pll->info->name, pipe_name(crtc->pipe), pll->active_mask); in verify_single_dpll_state()
4660 I915_STATE_WARN(i915, !(pll->state.pipe_mask & pipe_mask), in verify_single_dpll_state()
4661 "%s: pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n", in verify_single_dpll_state()
4662 pll->info->name, pipe_mask, pll->state.pipe_mask); in verify_single_dpll_state()
4665 pll->on && memcmp(&pll->state.hw_state, &dpll_hw_state, in verify_single_dpll_state()
4667 "%s: pll hw state mismatch\n", in verify_single_dpll_state()
4668 pll->info->name); in verify_single_dpll_state()
4675 (old_pll->info->is_alt_port_dpll || new_pll->info->is_alt_port_dpll); in has_alt_port_dpll()
4681 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_shared_dpll_state_verify()
4687 if (new_crtc_state->shared_dpll) in intel_shared_dpll_state_verify()
4688 verify_single_dpll_state(i915, new_crtc_state->shared_dpll, in intel_shared_dpll_state_verify()
4691 if (old_crtc_state->shared_dpll && in intel_shared_dpll_state_verify()
4692 old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) { in intel_shared_dpll_state_verify()
4693 u8 pipe_mask = BIT(crtc->pipe); in intel_shared_dpll_state_verify()
4694 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll; in intel_shared_dpll_state_verify() local
4696 I915_STATE_WARN(i915, pll->active_mask & pipe_mask, in intel_shared_dpll_state_verify()
4697 "%s: pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n", in intel_shared_dpll_state_verify()
4698 pll->info->name, pipe_name(crtc->pipe), pll->active_mask); in intel_shared_dpll_state_verify()
4700 /* TC ports have both MG/TC and TBT PLL referenced simultaneously */ in intel_shared_dpll_state_verify()
4701 I915_STATE_WARN(i915, !has_alt_port_dpll(old_crtc_state->shared_dpll, in intel_shared_dpll_state_verify()
4702 new_crtc_state->shared_dpll) && in intel_shared_dpll_state_verify()
4703 pll->state.pipe_mask & pipe_mask, in intel_shared_dpll_state_verify()
4704 "%s: pll enabled crtcs mismatch (found pipe %c in enabled mask (0x%x))\n", in intel_shared_dpll_state_verify()
4705 pll->info->name, pipe_name(crtc->pipe), pll->state.pipe_mask); in intel_shared_dpll_state_verify()
4711 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_shared_dpll_verify_disabled()
4712 struct intel_shared_dpll *pll; in intel_shared_dpll_verify_disabled() local
4715 for_each_shared_dpll(i915, pll, i) in intel_shared_dpll_verify_disabled()
4716 verify_single_dpll_state(i915, pll, NULL, NULL); in intel_shared_dpll_verify_disabled()