Lines Matching +full:pll +full:- +full:out
1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk-provider.h>
42 #define WISR_PLLLS BIT(8) /* PLL Lock Status */
49 #define DSI_WRPCR 0x0430 /* Wrapper Regulator & Pll Ctrl Reg */
50 #define WRPCR_PLLEN BIT(0) /* PLL ENable */
51 #define WRPCR_NDIV GENMASK(8, 2) /* pll loop DIVision Factor */
52 #define WRPCR_IDF GENMASK(14, 11) /* pll Input Division Factor */
53 #define WRPCR_ODF GENMASK(17, 16) /* pll Output Division Factor */
76 /* Sleep & timeout for regulator on/off, pll lock/unlock & fifo empty */
96 writel(val, dsi->base + reg); in dsi_write()
101 return readl(dsi->base + reg); in dsi_read()
157 return -EINVAL; in dsi_pll_get_params()
159 fvco_min = dsi->lane_min_kbps * 2 * ODF_MAX; in dsi_pll_get_params()
160 fvco_max = dsi->lane_max_kbps * 2 * ODF_MIN; in dsi_pll_get_params()
185 delta = dsi_pll_get_clkout_khz(clkin_khz, i, n, o) - in dsi_pll_get_params()
188 delta = -delta; in dsi_pll_get_params()
213 /* Disable the DSI PLL */ in dw_mipi_dsi_clk_disable()
230 ret = readl_poll_timeout_atomic(dsi->base + DSI_WISR, val, val & WISR_RRS, in dw_mipi_dsi_clk_enable()
235 /* Enable the DSI PLL & wait for its lock */ in dw_mipi_dsi_clk_enable()
237 ret = readl_poll_timeout_atomic(dsi->base + DSI_WISR, val, val & WISR_PLLLS, in dw_mipi_dsi_clk_enable()
240 DRM_DEBUG_DRIVER("!TIMEOUT! waiting PLL, let's continue\n"); in dw_mipi_dsi_clk_enable()
271 /* Get the adjusted pll out value */ in dw_mipi_dsi_clk_recalc_rate()
288 /* Compute best pll parameters */ in dw_mipi_dsi_clk_round_rate()
298 /* Get the adjusted pll out value */ in dw_mipi_dsi_clk_round_rate()
316 /* Compute best pll parameters */ in dw_mipi_dsi_clk_set_rate()
325 /* Get the adjusted pll out value */ in dw_mipi_dsi_clk_set_rate()
328 /* Set the PLL division factors */ in dw_mipi_dsi_clk_set_rate()
330 (ndiv << 2) | (idf << 11) | ((ffs(odf) - 1) << 16)); in dw_mipi_dsi_clk_set_rate()
332 /* Compute uix4 & set the bit period in high-speed mode */ in dw_mipi_dsi_clk_set_rate()
345 of_clk_del_provider(dsi->dev->of_node); in dw_mipi_dsi_clk_unregister()
346 clk_hw_unregister(&dsi->txbyte_clk); in dw_mipi_dsi_clk_unregister()
368 struct device_node *node = dev->of_node; in dw_mipi_dsi_clk_register()
373 dsi->txbyte_clk.init = &cdata_init; in dw_mipi_dsi_clk_register()
375 ret = clk_hw_register(dev, &dsi->txbyte_clk); in dw_mipi_dsi_clk_register()
380 &dsi->txbyte_clk); in dw_mipi_dsi_clk_register()
382 clk_hw_unregister(&dsi->txbyte_clk); in dw_mipi_dsi_clk_register()
392 ret = clk_prepare_enable(dsi->txbyte_clk.clk); in dw_mipi_dsi_phy_init()
412 clk_disable_unprepare(dsi->txbyte_clk.clk); in dw_mipi_dsi_phy_power_off()
427 pll_in_khz = (unsigned int)(clk_get_rate(dsi->pllref_clk) / 1000); in dw_mipi_dsi_get_lane_mbps()
429 /* Compute requested pll out */ in dw_mipi_dsi_get_lane_mbps()
431 pll_out_khz = mode->clock * bpp / lanes; in dw_mipi_dsi_get_lane_mbps()
433 /* Add 20% to pll out to be higher than pixel bw (burst mode only) */ in dw_mipi_dsi_get_lane_mbps()
437 if (pll_out_khz > dsi->lane_max_kbps) { in dw_mipi_dsi_get_lane_mbps()
438 pll_out_khz = dsi->lane_max_kbps; in dw_mipi_dsi_get_lane_mbps()
441 if (pll_out_khz < dsi->lane_min_kbps) { in dw_mipi_dsi_get_lane_mbps()
442 pll_out_khz = dsi->lane_min_kbps; in dw_mipi_dsi_get_lane_mbps()
446 ret = clk_set_rate((dsi->txbyte_clk.clk), pll_out_khz * 1000); in dw_mipi_dsi_get_lane_mbps()
448 DRM_DEBUG_DRIVER("ERROR Could not set rate of %d to %s clk->name", in dw_mipi_dsi_get_lane_mbps()
449 pll_out_khz, clk_hw_get_name(&dsi->txbyte_clk)); in dw_mipi_dsi_get_lane_mbps()
479 timing->clk_hs2lp = DSI_PHY_DELAY(272, 136, lane_mbps); in dw_mipi_dsi_phy_get_timing()
480 timing->clk_lp2hs = DSI_PHY_DELAY(512, 40, lane_mbps); in dw_mipi_dsi_phy_get_timing()
481 timing->data_hs2lp = DSI_PHY_DELAY(192, 64, lane_mbps); in dw_mipi_dsi_phy_get_timing()
482 timing->data_lp2hs = DSI_PHY_DELAY(256, 32, lane_mbps); in dw_mipi_dsi_phy_get_timing()
502 /* Compute requested pll out */ in dw_mipi_dsi_stm_mode_valid()
503 pll_out_khz = mode->clock * bpp / lanes; in dw_mipi_dsi_stm_mode_valid()
505 if (pll_out_khz > dsi->lane_max_kbps) in dw_mipi_dsi_stm_mode_valid()
509 /* Add 20% to pll out to be higher than pixel bw */ in dw_mipi_dsi_stm_mode_valid()
512 if (pll_out_khz < dsi->lane_min_kbps) in dw_mipi_dsi_stm_mode_valid()
516 /* Compute best pll parameters */ in dw_mipi_dsi_stm_mode_valid()
520 pll_in_khz = clk_get_rate(dsi->pllref_clk) / 1000; in dw_mipi_dsi_stm_mode_valid()
532 /* Get the adjusted pll out value */ in dw_mipi_dsi_stm_mode_valid()
536 target_px_clock_hz = mode->clock * 1000; in dw_mipi_dsi_stm_mode_valid()
541 if (px_clock_hz < target_px_clock_hz - CLK_TOLERANCE_HZ || in dw_mipi_dsi_stm_mode_valid()
548 hfp = mode->hsync_start - mode->hdisplay; in dw_mipi_dsi_stm_mode_valid()
549 hsync = mode->hsync_end - mode->hsync_start; in dw_mipi_dsi_stm_mode_valid()
550 hbp = mode->htotal - mode->hsync_end; in dw_mipi_dsi_stm_mode_valid()
560 hbp -= dsi_short_packet_size_px; in dw_mipi_dsi_stm_mode_valid()
563 hbp += hsync - dsi_short_packet_size_px; in dw_mipi_dsi_stm_mode_valid()
571 * In non-burst mode DSI has to enter in LP during HFP in dw_mipi_dsi_stm_mode_valid()
599 { .compatible = "st,stm32-dsi", .data = &dw_mipi_dsi_stm_plat_data, },
606 struct device *dev = &pdev->dev; in dw_mipi_dsi_stm_probe()
613 return -ENOMEM; in dw_mipi_dsi_stm_probe()
615 dsi->base = devm_platform_ioremap_resource(pdev, 0); in dw_mipi_dsi_stm_probe()
616 if (IS_ERR(dsi->base)) { in dw_mipi_dsi_stm_probe()
617 ret = PTR_ERR(dsi->base); in dw_mipi_dsi_stm_probe()
622 dsi->vdd_supply = devm_regulator_get(dev, "phy-dsi"); in dw_mipi_dsi_stm_probe()
623 if (IS_ERR(dsi->vdd_supply)) { in dw_mipi_dsi_stm_probe()
624 ret = PTR_ERR(dsi->vdd_supply); in dw_mipi_dsi_stm_probe()
629 ret = regulator_enable(dsi->vdd_supply); in dw_mipi_dsi_stm_probe()
635 dsi->pllref_clk = devm_clk_get(dev, "ref"); in dw_mipi_dsi_stm_probe()
636 if (IS_ERR(dsi->pllref_clk)) { in dw_mipi_dsi_stm_probe()
637 ret = PTR_ERR(dsi->pllref_clk); in dw_mipi_dsi_stm_probe()
638 dev_err_probe(dev, ret, "Unable to get pll reference clock\n"); in dw_mipi_dsi_stm_probe()
642 ret = clk_prepare_enable(dsi->pllref_clk); in dw_mipi_dsi_stm_probe()
648 dsi->pclk = devm_clk_get(dev, "pclk"); in dw_mipi_dsi_stm_probe()
649 if (IS_ERR(dsi->pclk)) { in dw_mipi_dsi_stm_probe()
650 ret = PTR_ERR(dsi->pclk); in dw_mipi_dsi_stm_probe()
655 ret = clk_prepare_enable(dsi->pclk); in dw_mipi_dsi_stm_probe()
661 dsi->hw_version = dsi_read(dsi, DSI_VERSION) & VERSION; in dw_mipi_dsi_stm_probe()
662 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_stm_probe()
664 if (dsi->hw_version != HWVER_130 && dsi->hw_version != HWVER_131) { in dw_mipi_dsi_stm_probe()
665 ret = -ENODEV; in dw_mipi_dsi_stm_probe()
671 dsi->lane_min_kbps = LANE_MIN_KBPS; in dw_mipi_dsi_stm_probe()
672 dsi->lane_max_kbps = LANE_MAX_KBPS; in dw_mipi_dsi_stm_probe()
673 if (dsi->hw_version == HWVER_131) { in dw_mipi_dsi_stm_probe()
674 dsi->lane_min_kbps *= 2; in dw_mipi_dsi_stm_probe()
675 dsi->lane_max_kbps *= 2; in dw_mipi_dsi_stm_probe()
678 dsi->pdata = *pdata; in dw_mipi_dsi_stm_probe()
679 dsi->pdata.base = dsi->base; in dw_mipi_dsi_stm_probe()
680 dsi->pdata.priv_data = dsi; in dw_mipi_dsi_stm_probe()
682 dsi->pdata.max_data_lanes = 2; in dw_mipi_dsi_stm_probe()
683 dsi->pdata.phy_ops = &dw_mipi_dsi_stm_phy_ops; in dw_mipi_dsi_stm_probe()
687 dsi->dsi = dw_mipi_dsi_probe(pdev, &dsi->pdata); in dw_mipi_dsi_stm_probe()
688 if (IS_ERR(dsi->dsi)) { in dw_mipi_dsi_stm_probe()
689 ret = PTR_ERR(dsi->dsi); in dw_mipi_dsi_stm_probe()
698 ret = clk_prepare_enable(dsi->pclk); in dw_mipi_dsi_stm_probe()
707 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_stm_probe()
711 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_stm_probe()
716 clk_disable_unprepare(dsi->pllref_clk); in dw_mipi_dsi_stm_probe()
718 regulator_disable(dsi->vdd_supply); in dw_mipi_dsi_stm_probe()
727 dw_mipi_dsi_remove(dsi->dsi); in dw_mipi_dsi_stm_remove()
728 clk_disable_unprepare(dsi->pllref_clk); in dw_mipi_dsi_stm_remove()
730 regulator_disable(dsi->vdd_supply); in dw_mipi_dsi_stm_remove()
739 clk_disable_unprepare(dsi->pllref_clk); in dw_mipi_dsi_stm_suspend()
740 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_stm_suspend()
741 regulator_disable(dsi->vdd_supply); in dw_mipi_dsi_stm_suspend()
753 ret = regulator_enable(dsi->vdd_supply); in dw_mipi_dsi_stm_resume()
759 ret = clk_prepare_enable(dsi->pclk); in dw_mipi_dsi_stm_resume()
761 regulator_disable(dsi->vdd_supply); in dw_mipi_dsi_stm_resume()
766 ret = clk_prepare_enable(dsi->pllref_clk); in dw_mipi_dsi_stm_resume()
768 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_stm_resume()
769 regulator_disable(dsi->vdd_supply); in dw_mipi_dsi_stm_resume()
789 .name = "stm32-display-dsi",