Lines Matching +full:pll +full:- +full:out
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
27 #include "pll.h"
31 #include <subdev/bios/pll.h>
45 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
50 return device->crystal; in read_vco()
63 struct nvkm_device *device = clk->base.subdev.device; in read_clk()
68 if (device->chipset == 0xaf) { in read_clk()
73 return device->crystal; in read_clk()
88 return device->crystal; in read_clk()
108 read_pll(struct gt215_clk *clk, int idx, u32 pll) in read_pll() argument
110 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
111 u32 ctrl = nvkm_rd32(device, pll + 0); in read_pll()
117 u32 coef = nvkm_rd32(device, pll + 4); in read_pll()
122 /* no post-divider on these.. in read_pll()
123 * XXX: it looks more like two post-"dividers" that in read_pll()
124 * cross each other out in the default RPLL config */ in read_pll()
125 if ((pll & 0x00ff00) == 0x00e800) in read_pll()
146 struct nvkm_subdev *subdev = &clk->base.subdev; in gt215_clk_read()
147 struct nvkm_device *device = subdev->device; in gt215_clk_read()
152 return device->crystal; in gt215_clk_read()
176 return -EINVAL; in gt215_clk_read()
180 return -EINVAL; in gt215_clk_read()
194 info->clk = 0; in gt215_clk_info()
198 info->clk = 0x00000100; in gt215_clk_info()
201 info->clk = 0x00002100; in gt215_clk_info()
204 info->clk = 0x00002140; in gt215_clk_info()
210 diff = ((khz + 3000) - oclk); in gt215_clk_info()
220 * and the VBIOS on my NVA8 seem to prefer using the PLL in gt215_clk_info()
221 * for 810MHz - is there a good reason? in gt215_clk_info()
224 info->clk = (((sdiv - 2) << 16) | 0x00003100); in gt215_clk_info()
231 return -ERANGE; in gt215_clk_info()
235 gt215_pll_info(struct nvkm_clk *base, int idx, u32 pll, u32 khz, in gt215_pll_info() argument
239 struct nvkm_subdev *subdev = &clk->base.subdev; in gt215_pll_info()
244 info->pll = 0; in gt215_pll_info()
246 /* If we can get a within [-2, 3) MHz of a divider, we'll disable the in gt215_pll_info()
247 * PLL and use the divider instead. */ in gt215_pll_info()
248 ret = gt215_clk_info(&clk->base, idx, khz, info); in gt215_pll_info()
249 diff = khz - ret; in gt215_pll_info()
250 if (!pll || (diff >= -2000 && diff < 3000)) { in gt215_pll_info()
251 goto out; in gt215_pll_info()
254 /* Try with PLL */ in gt215_pll_info()
255 ret = nvbios_pll_parse(subdev->device->bios, pll, &limits); in gt215_pll_info()
259 ret = gt215_clk_info(&clk->base, idx - 0x10, limits.refclk, info); in gt215_pll_info()
261 return -EINVAL; in gt215_pll_info()
265 info->pll = (P << 16) | (N << 8) | M; in gt215_pll_info()
268 out: in gt215_pll_info()
269 info->fb_delay = max(((khz + 7566) / 15133), (u32) 18); in gt215_pll_info()
270 return ret ? ret : -ERANGE; in gt215_pll_info()
275 int idx, u32 pll, int dom) in calc_clk() argument
277 int ret = gt215_pll_info(&clk->base, idx, pll, cstate->domain[dom], in calc_clk()
278 &clk->eng[dom]); in calc_clk()
288 u32 kHz = cstate->domain[nv_clk_src_host]; in calc_host()
289 struct gt215_clk_info *info = &clk->eng[nv_clk_src_host]; in calc_host()
292 info->clk = 0; in calc_host()
293 info->host_out = NVA3_HOST_277; in calc_host()
297 info->host_out = NVA3_HOST_CLK; in calc_host()
299 ret = gt215_clk_info(&clk->base, 0x1d, kHz, info); in calc_host()
309 struct nvkm_device *device = clk->subdev.device; in gt215_clk_pre()
310 struct nvkm_fifo *fifo = device->fifo; in gt215_clk_pre()
320 return -EBUSY; in gt215_clk_pre()
329 return -EIO; in gt215_clk_pre()
336 return -EIO; in gt215_clk_pre()
344 struct nvkm_device *device = clk->subdev.device; in gt215_clk_post()
345 struct nvkm_fifo *fifo = device->fifo; in gt215_clk_post()
357 struct nvkm_device *device = clk->base.subdev.device; in disable_clk_src()
363 prog_pll(struct gt215_clk *clk, int idx, u32 pll, int dom) in prog_pll() argument
365 struct gt215_clk_info *info = &clk->eng[dom]; in prog_pll()
366 struct nvkm_device *device = clk->base.subdev.device; in prog_pll()
369 const u32 ctrl = pll + 0; in prog_pll()
370 const u32 coef = pll + 4; in prog_pll()
373 if (info->pll) { in prog_pll()
374 /* Always start from a non-PLL clock */ in prog_pll()
382 nvkm_mask(device, src0, 0x003f3141, 0x00000101 | info->clk); in prog_pll()
383 nvkm_wr32(device, coef, info->pll); in prog_pll()
398 nvkm_mask(device, src1, 0x003f3141, 0x00000101 | info->clk); in prog_pll()
409 struct gt215_clk_info *info = &clk->eng[dom]; in prog_clk()
410 struct nvkm_device *device = clk->base.subdev.device; in prog_clk()
411 nvkm_mask(device, 0x004120 + (idx * 4), 0x003f3141, 0x00000101 | info->clk); in prog_clk()
417 struct gt215_clk_info *info = &clk->eng[nv_clk_src_host]; in prog_host()
418 struct nvkm_device *device = clk->base.subdev.device; in prog_host()
421 switch (info->host_out) { in prog_host()
445 struct gt215_clk_info *info = &clk->eng[dom]; in prog_core()
446 struct nvkm_device *device = clk->base.subdev.device; in prog_core()
449 if (fb_delay < info->fb_delay) in prog_core()
450 nvkm_wr32(device, 0x10002c, info->fb_delay); in prog_core()
454 if (fb_delay > info->fb_delay) in prog_core()
455 nvkm_wr32(device, 0x10002c, info->fb_delay); in prog_core()
462 struct gt215_clk_info *core = &clk->eng[nv_clk_src_core]; in gt215_clk_calc()
473 * whether to use a PLL or not... but using a PLL defeats the purpose */ in gt215_clk_calc()
474 if (core->pll) { in gt215_clk_calc()
475 ret = gt215_clk_info(&clk->base, 0x10, in gt215_clk_calc()
476 cstate->domain[nv_clk_src_core_intm], in gt215_clk_calc()
477 &clk->eng[nv_clk_src_core_intm]); in gt215_clk_calc()
489 struct gt215_clk_info *core = &clk->eng[nv_clk_src_core]; in gt215_clk_prog()
494 ret = gt215_clk_pre(&clk->base, f); in gt215_clk_prog()
496 goto out; in gt215_clk_prog()
498 if (core->pll) in gt215_clk_prog()
507 out: in gt215_clk_prog()
508 if (ret == -EBUSY) in gt215_clk_prog()
511 gt215_clk_post(&clk->base, f); in gt215_clk_prog()
546 return -ENOMEM; in gt215_clk_new()
547 *pclk = &clk->base; in gt215_clk_new()
549 return nvkm_clk_ctor(>215_clk, device, type, inst, true, &clk->base); in gt215_clk_new()