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/linux-6.12.1/Documentation/devicetree/bindings/net/
Dmotorcomm,yt8xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Sae <frank.sae@motor-comm.com>
13 - $ref: ethernet-phy.yaml#
18 - ethernet-phy-id4f51.e91a
19 - ethernet-phy-id4f51.e91b
21 rx-internal-delay-ps:
24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
30 tx-internal-delay-ps:
[all …]
Dqca,ar803x.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
18 - $ref: ethernet-phy.yaml#
21 qca,clk-out-frequency:
26 qca,clk-out-strength:
31 qca,disable-smarteee:
[all …]
/linux-6.12.1/drivers/clk/meson/
Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0
11 * In the most basic form, a Meson PLL is composed as follows:
13 * PLL
14 * +--------------------------------+
16 * | +--+ |
17 * in >>-----[ /N ]--->| | +-----+ |
18 * | | |------| DCO |---->> out
19 * | +--------->| | +--v--+ |
20 * | | +--+ | |
22 * | +--[ *(M + (F/Fmax) ]<--+ |
[all …]
/linux-6.12.1/arch/arm64/boot/dts/rockchip/
Drk3328-nanopi-r2c.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
9 /dts-v1/;
10 #include "rk3328-nanopi-r2s.dts"
14 compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328";
18 phy-handle = <&yt8521s>;
23 /delete-node/ ethernet-phy@1;
25 yt8521s: ethernet-phy@3 {
26 compatible = "ethernet-phy-ieee802.3-c22";
29 motorcomm,clk-out-frequency-hz = <125000000>;
[all …]
Drk3328-orangepi-r1-plus-lts.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
9 /dts-v1/;
10 #include "rk3328-orangepi-r1-plus.dts"
14 compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
18 phy-handle = <&yt8531c>;
23 /delete-node/ ethernet-phy@1;
25 yt8531c: ethernet-phy@0 {
26 compatible = "ethernet-phy-ieee802.3-c22";
29 motorcomm,auto-sleep-disabled;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dfsl-ls1028a-kontron-sl28-var4.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Device Tree file for the Kontron SMARC-sAL28 board.
12 /dts-v1/;
13 #include "fsl-ls1028a-kontron-sl28.dts"
14 #include <dt-bindings/net/qca-ar803x.h>
17 model = "Kontron SMARC-sAL28 (Dual PHY)";
18 compatible = "kontron,sl28-var4", "kontron,sl28", "fsl,ls1028a";
22 phy1: ethernet-phy@4 {
24 eee-broken-1000t;
25 eee-broken-100tx;
[all …]
Dfsl-ls1028a-kontron-sl28-var1.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Device Tree file for the Kontron SMARC-sAL28 board.
15 /dts-v1/;
16 #include "fsl-ls1028a-kontron-sl28.dts"
17 #include <dt-bindings/net/qca-ar803x.h>
20 model = "Kontron SMARC-sAL28 (4 Lanes)";
21 compatible = "kontron,sl28-var1", "kontron,sl28", "fsl,ls1028a";
26 /delete-node/ ethernet-phy@5;
28 phy0: ethernet-phy@4 {
30 eee-broken-1000t;
[all …]
/linux-6.12.1/drivers/clk/at91/
Dsam9x7.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/clk-provider.h>
15 #include <dt-bindings/clock/at91.h>
23 * enum pll_ids - PLL clocks identifiers
26 * @PLL_ID_AUDIO: Audio PLL identifier
27 * @PLL_ID_LVDS: LVDS PLL identifier
29 * @PLL_ID_MAX: Max PLL Identifier
41 * enum pll_type - PLL type identifiers
42 * @PLL_TYPE_FRAC: fractional PLL identifier
43 * @PLL_TYPE_DIV: divider PLL identifier
[all …]
Ddt-compat.c1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
33 const char *name = np->name; in of_sama5d2_clk_audio_pll_frac_setup()
53 "atmel,sama5d2-clk-audio-pll-frac",
59 const char *name = np->name; in of_sama5d2_clk_audio_pll_pad_setup()
79 "atmel,sama5d2-clk-audio-pll-pad",
85 const char *name = np->name; in of_sama5d2_clk_audio_pll_pmc_setup()
105 "atmel,sama5d2-clk-audio-pll-pmc",
161 if (of_property_read_string(np, "clock-output-names", &name)) in of_sama5d2_clk_generated_setup()
162 name = gcknp->name; in of_sama5d2_clk_generated_setup()
[all …]
Dsam9x60.c1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
6 #include <dt-bindings/clock/at91.h>
29 /* Fractional PLL core output range. */
89 * ddrck feeds DDR controller and is enabled by bootloader thus we need
90 * to keep it enabled in case there is no Linux consumer for it.
149 * mpddr_clk feeds DDR controller and is enabled by bootloader thus we
150 * need to keep it enabled in case there is no Linux consumer for it.
196 i = of_property_match_string(np, "clock-names", "td_slck"); in sam9x60_pmc_setup()
202 i = of_property_match_string(np, "clock-names", "md_slck"); in sam9x60_pmc_setup()
[all …]
/linux-6.12.1/drivers/net/phy/qcom/
Dat803x.c1 // SPDX-License-Identifier: GPL-2.0+
23 #include <dt-bindings/net/qca-ar803x.h>
48 #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/
55 /* AT803x supports either the XTAL input pad, an internal PLL or the
57 * is only used for 25 MHz output, all other frequencies need the PLL.
61 * By default the PLL is only enabled if there is a link. Otherwise
62 * the PHY will go into low power state and disabled the PLL. You can
63 * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always
64 * enabled.
78 * but doesn't support choosing between XTAL/PLL and DSP.
[all …]
/linux-6.12.1/drivers/gpu/drm/bridge/
Dtc358768.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com
13 #include <linux/media-bus-format.h>
29 /* Global (16-bit addressable) */
46 /* Debug (16-bit addressable) */
52 /* TX PHY (32-bit addressable) */
64 /* TX PPI (32-bit addressable) */
80 /* TX CTRL (32-bit addressable) */
101 /* DSITX CTRL (16-bit addressable) */
147 int enabled; member
[all …]
/linux-6.12.1/drivers/gpu/drm/renesas/rcar-du/
Drcar_lvds.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car LVDS Encoder
5 * Copyright (C) 2013-2018 Renesas Electronics Corporation
13 #include <linux/media-bus-format.h>
37 /* Keep in sync with the LVDCR0.LVMD hardware register values. */
53 #define RCAR_LVDS_QUIRK_EXT_PLL BIT(3) /* Has extended PLL */
54 #define RCAR_LVDS_QUIRK_DUAL_LINK BIT(4) /* Supports dual-link operation */
88 return ioread32(lvds->mmio + reg); in rcar_lvds_read()
93 iowrite32(data, lvds->mmio + reg); in rcar_lvds_write()
96 /* -----------------------------------------------------------------------------
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/net/dsa/
Dqca8k.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - John Crispin <john@phrozen.org>
13 If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
16 ID. To declare the internal mdio-bus configuration, declare an MDIO node in
18 PHY it is connected to. In this config, an internal mdio-bus is registered and
20 mdio-bus configurations are not supported by the hardware.
27 - enum:
28 - qca,qca8327
[all …]
/linux-6.12.1/drivers/gpu/drm/radeon/
Dradeon_legacy_crtc.c2 * Copyright 2007-8 Advanced Micro Devices, Inc.
40 struct drm_device *dev = crtc->dev; in radeon_overscan_setup()
41 struct radeon_device *rdev = dev->dev_private; in radeon_overscan_setup()
44 WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup()
45 WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup()
46 WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup()
52 struct drm_device *dev = crtc->dev; in radeon_legacy_rmx_mode_set()
53 struct radeon_device *rdev = dev->dev_private; in radeon_legacy_rmx_mode_set()
55 int xres = mode->hdisplay; in radeon_legacy_rmx_mode_set()
56 int yres = mode->vdisplay; in radeon_legacy_rmx_mode_set()
[all …]
/linux-6.12.1/Documentation/driver-api/media/
Dcamera-sensor.rst1 .. SPDX-License-Identifier: GPL-2.0
8 This document covers the in-kernel APIs only. For the best practices on
12 CSI-2, parallel and BT.656 buses
13 --------------------------------
15 Please see :ref:`transmitter-receiver`.
18 ---------------
20 Camera sensors have an internal clock tree including a PLL and a number of
29 elsewhere. Therefore only the pre-determined frequencies are configurable by the
35 Read the ``clock-frequency`` _DSD property to denote the frequency. The driver
41 The preferred way to achieve this is using ``assigned-clocks``,
[all …]
/linux-6.12.1/drivers/clk/samsung/
Dclk-exynos-arm64.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include "clk-exynos-arm64.h"
20 /* PLL register bits */
67 * exynos_arm64_init_clocks - Set clocks initial configuration
71 * Set manual control mode for all gate and PLL clocks.
76 const unsigned long *reg_offs = cmu->clk_regs; in exynos_arm64_init_clocks()
77 size_t reg_offs_len = cmu->nr_clk_regs; in exynos_arm64_init_clocks()
89 if (cmu->manual_plls && is_pll_con1_reg(reg_offs[i])) { in exynos_arm64_init_clocks()
103 * exynos_arm64_enable_bus_clk - Enable parent clock of specified CMU
110 * Keep CMU parent clock running (needed for CMU registers access).
[all …]
/linux-6.12.1/include/linux/habanalabs/
Dhl_boot_if.h1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2018-2023 HabanaLabs, Ltd.
11 #define LKD_HARD_RESET_MAGIC 0xED7BD694 /* deprecated - do not use */
47 * will clear the non-relevant ones.
67 * Boot continues as usual, but keep in
89 * started, but is not ready yet - chip
114 * CPU_BOOT_ERR0_PLL_FAIL PLL settings failed, meaning that one
139 * CPU_BOOT_ERR0_ENABLED Error registers enabled.
206 * CPU_BOOT_DEV_STS0_SECURITY_EN Security is Enabled.
208 * enabled in FW, which means that
[all …]
/linux-6.12.1/drivers/clk/st/
Dclkgen-fsyn.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/clk-provider.h>
20 * Maximum input clock to the PLL before we divide it down by 2
129 { .name = "clk-s-c0-fs0-ch0", },
130 { .name = "clk-s-c0-fs0-ch1", },
131 { .name = "clk-s-c0-fs0-ch2", },
132 { .name = "clk-s-c0-fs0-ch3", },
186 { .name = "clk-s-d0-fs0-ch0", },
187 { .name = "clk-s-d0-fs0-ch1", },
188 { .name = "clk-s-d0-fs0-ch2", },
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/
Ddce_clk_mgr.c2 * Copyright 2012-16 Advanced Micro Devices, Inc.
47 (clk_mgr->regs->reg)
51 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
68 /* ClocksStateInvalid - should not be used */
70 /* ClocksStateUltraLow - not expected to be used for DCE 8.0 */
88 * (did - DENTIST_BASE_DID_1); in dentist_get_divider_from_did()
91 * (did - DENTIST_BASE_DID_2); in dentist_get_divider_from_did()
94 * (did - DENTIST_BASE_DID_3); in dentist_get_divider_from_did()
97 * (did - DENTIST_BASE_DID_4); in dentist_get_divider_from_did()
104 -if SS enabled on DP Ref clock and HW de-spreading enabled with SW
[all …]
/linux-6.12.1/Documentation/driver-api/thermal/
Dintel_dptf.rst1 .. SPDX-License-Identifier: GPL-2.0
12 ------------
31 ----------------------------
43 "42A441D6-AE6A-462b-A84B-4A8CE79027D3" : Passive 1
45 "3A95C389-E4B8-4629-A526-C52C88626BAE" : Active
47 "97C68AE7-15FA-499c-B8C9-5DA81D606E0A" : Critical
49 "63BE270F-1C11-48FD-A6F7-3AF253FF3E2D" : Adaptive performance
51 "5349962F-71E6-431D-9AE8-0A635B710AEE" : Emergency call
53 "9E04115A-AE87-4D1C-9500-0F3E340BFE75" : Passive 2
55 "F5A35014-C209-46A4-993A-EB56DE7530A1" : Power Boss
[all …]
/linux-6.12.1/drivers/net/wireless/broadcom/b43/
Db43.h1 /* SPDX-License-Identifier: GPL-2.0 */
61 /* 32-bit DMA */
68 /* 64-bit DMA */
203 #define B43_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
209 #define B43_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
211 #define B43_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
212 #define B43_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */
234 #define B43_SHM_AUTOINC_R 0x0200 /* Auto-increment address on read */
235 #define B43_SHM_AUTOINC_W 0x0100 /* Auto-increment address on write */
330 #define B43_SHM_SH_SPUWKUP 0x0094 /* pre-wakeup for synth PU in us */
[all …]
/linux-6.12.1/drivers/phy/broadcom/
Dphy-brcm-usb-init.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * phy-brcm-usb-init.c - Broadcom USB Phy chip specific init functions
5 * Copyright (C) 2014-2017 Broadcom
16 #include "phy-brcm-usb-init.h"
142 (params->usb_reg_bits_map[USB_CTRL_##reg##_##field##_SELECTOR])
455 mask = params->usb_reg_bits_map[field]; in usb_ctrl_unset_family()
456 brcm_usb_ctrl_unset(params->regs[BRCM_REGS_CTRL] + reg_offset, mask); in usb_ctrl_unset_family()
465 mask = params->usb_reg_bits_map[field]; in usb_ctrl_set_family()
466 brcm_usb_ctrl_set(params->regs[BRCM_REGS_CTRL] + reg_offset, mask); in usb_ctrl_set_family()
512 /* reset USB 2.0 PLL */ in brcmusb_usb_phy_ldo_fix()
[all …]
/linux-6.12.1/drivers/gpu/drm/i915/display/
Dintel_dpll.c1 // SPDX-License-Identifier: MIT
196 * the range value for them is (actual_value - 2).
308 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
309 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
313 * divided-down version of it.
318 clock->m = clock->m2 + 2; in pnv_calc_dpll_params()
319 clock->p = clock->p1 * clock->p2; in pnv_calc_dpll_params()
321 clock->vco = clock->n == 0 ? 0 : in pnv_calc_dpll_params()
322 DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); in pnv_calc_dpll_params()
323 clock->dot = clock->p == 0 ? 0 : in pnv_calc_dpll_params()
[all …]
/linux-6.12.1/include/linux/bcma/
Dbcma_driver_chipcommon.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 #define BCMA_CC_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
34 #define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */
49 #define BCMA_CC_CAP_64BIT 0x08000000 /* 64-bit Backplane */
103 #define BCMA_CC_CHIPST_4706_PKG_OPTION BIT(0) /* 0: full-featured package 1: low-cost package */
105 #define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
154 #define BCMA_CC_FLASHCTL_ST_DP 0x00b9 /* Deep Power-down */
156 #define BCMA_CC_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */
157 #define BCMA_CC_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
235 #define BCMA_CC_SLOWCLKCTL_LPOPD 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled…
[all …]

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