Lines Matching +full:keep +full:- +full:pll +full:- +full:enabled
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
40 struct drm_device *dev = crtc->dev; in radeon_overscan_setup()
41 struct radeon_device *rdev = dev->dev_private; in radeon_overscan_setup()
44 WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup()
45 WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup()
46 WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup()
52 struct drm_device *dev = crtc->dev; in radeon_legacy_rmx_mode_set()
53 struct radeon_device *rdev = dev->dev_private; in radeon_legacy_rmx_mode_set()
55 int xres = mode->hdisplay; in radeon_legacy_rmx_mode_set()
56 int yres = mode->vdisplay; in radeon_legacy_rmx_mode_set()
66 struct drm_display_mode *native_mode = &radeon_crtc->native_mode; in radeon_legacy_rmx_mode_set()
76 if ((rdev->family == CHIP_RS100) || in radeon_legacy_rmx_mode_set()
77 (rdev->family == CHIP_RS200)) { in radeon_legacy_rmx_mode_set()
84 fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff) in radeon_legacy_rmx_mode_set()
85 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); in radeon_legacy_rmx_mode_set()
87 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; in radeon_legacy_rmx_mode_set()
90 hsync_start = mode->crtc_hsync_start - 8; in radeon_legacy_rmx_mode_set()
94 | ((mode->flags & DRM_MODE_FLAG_NHSYNC) in radeon_legacy_rmx_mode_set()
98 fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff) in radeon_legacy_rmx_mode_set()
99 | ((mode->crtc_vdisplay - 1) << 16)); in radeon_legacy_rmx_mode_set()
101 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; in radeon_legacy_rmx_mode_set()
105 fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff) in radeon_legacy_rmx_mode_set()
107 | ((mode->flags & DRM_MODE_FLAG_NVSYNC) in radeon_legacy_rmx_mode_set()
113 if (native_mode->hdisplay == 0 || in radeon_legacy_rmx_mode_set()
114 native_mode->vdisplay == 0) { in radeon_legacy_rmx_mode_set()
118 if (xres > native_mode->hdisplay) in radeon_legacy_rmx_mode_set()
119 xres = native_mode->hdisplay; in radeon_legacy_rmx_mode_set()
120 if (yres > native_mode->vdisplay) in radeon_legacy_rmx_mode_set()
121 yres = native_mode->vdisplay; in radeon_legacy_rmx_mode_set()
123 if (xres == native_mode->hdisplay) in radeon_legacy_rmx_mode_set()
125 if (yres == native_mode->vdisplay) in radeon_legacy_rmx_mode_set()
129 switch (radeon_crtc->rmx_type) { in radeon_legacy_rmx_mode_set()
133 fp_horz_stretch |= ((xres/8-1) << 16); in radeon_legacy_rmx_mode_set()
137 / native_mode->hdisplay + 1; in radeon_legacy_rmx_mode_set()
141 ((native_mode->hdisplay/8-1) << 16)); in radeon_legacy_rmx_mode_set()
145 fp_vert_stretch |= ((yres-1) << 12); in radeon_legacy_rmx_mode_set()
149 / native_mode->vdisplay + 1; in radeon_legacy_rmx_mode_set()
153 ((native_mode->vdisplay-1) << 12)); in radeon_legacy_rmx_mode_set()
157 fp_horz_stretch |= ((xres/8-1) << 16); in radeon_legacy_rmx_mode_set()
158 fp_vert_stretch |= ((yres-1) << 12); in radeon_legacy_rmx_mode_set()
163 blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8; in radeon_legacy_rmx_mode_set()
168 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); in radeon_legacy_rmx_mode_set()
170 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; in radeon_legacy_rmx_mode_set()
174 fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff) in radeon_legacy_rmx_mode_set()
176 | ((mode->flags & DRM_MODE_FLAG_NHSYNC) in radeon_legacy_rmx_mode_set()
180 fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff) in radeon_legacy_rmx_mode_set()
181 | ((mode->crtc_vdisplay - 1) << 16)); in radeon_legacy_rmx_mode_set()
183 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; in radeon_legacy_rmx_mode_set()
187 fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff) in radeon_legacy_rmx_mode_set()
189 | ((mode->flags & DRM_MODE_FLAG_NVSYNC) in radeon_legacy_rmx_mode_set()
193 fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) | in radeon_legacy_rmx_mode_set()
194 (((native_mode->hdisplay / 8) & 0x1ff) << 16)); in radeon_legacy_rmx_mode_set()
198 fp_horz_stretch |= ((xres/8-1) << 16); in radeon_legacy_rmx_mode_set()
199 fp_vert_stretch |= ((yres-1) << 12); in radeon_legacy_rmx_mode_set()
215 struct radeon_device *rdev = dev->dev_private; in radeon_pll_wait_for_read_update_complete()
230 struct radeon_device *rdev = dev->dev_private; in radeon_pll_write_update()
241 struct radeon_device *rdev = dev->dev_private; in radeon_pll2_wait_for_read_update_complete()
257 struct radeon_device *rdev = dev->dev_private; in radeon_pll2_write_update()
278 * 3 parts, each part having a fixed PLL gain value. in radeon_compute_pll_gain()
300 struct drm_device *dev = crtc->dev; in radeon_crtc_dpms()
301 struct radeon_device *rdev = dev->dev_private; in radeon_crtc_dpms()
305 if (radeon_crtc->crtc_id) in radeon_crtc_dpms()
322 if (rdev->flags & RADEON_SINGLE_CRTC) in radeon_crtc_dpms()
327 radeon_crtc->enabled = true; in radeon_crtc_dpms()
330 if (radeon_crtc->crtc_id) in radeon_crtc_dpms()
337 if (dev->num_crtcs > radeon_crtc->crtc_id) in radeon_crtc_dpms()
344 if (dev->num_crtcs > radeon_crtc->crtc_id) in radeon_crtc_dpms()
346 if (radeon_crtc->crtc_id) in radeon_crtc_dpms()
353 radeon_crtc->enabled = false; in radeon_crtc_dpms()
377 struct drm_device *dev = crtc->dev; in radeon_crtc_do_set_base()
378 struct radeon_device *rdev = dev->dev_private; in radeon_crtc_do_set_base()
393 if (!atomic && !crtc->primary->fb) { in radeon_crtc_do_set_base()
401 target_fb = crtc->primary->fb; in radeon_crtc_do_set_base()
403 switch (target_fb->format->cpp[0] * 8) { in radeon_crtc_do_set_base()
424 obj = target_fb->obj[0]; in radeon_crtc_do_set_base()
448 if (!atomic && fb && fb != crtc->primary->fb) { in radeon_crtc_do_set_base()
452 old_rbo = gem_to_radeon_bo(fb->obj[0]); in radeon_crtc_do_set_base()
462 return -EINVAL; in radeon_crtc_do_set_base()
471 radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start; in radeon_crtc_do_set_base()
473 base -= radeon_crtc->legacy_display_base_addr; in radeon_crtc_do_set_base()
477 pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; in radeon_crtc_do_set_base()
478 crtc_pitch = DIV_ROUND_UP(pitch_pixels * target_fb->format->cpp[0] * 8, in radeon_crtc_do_set_base()
479 target_fb->format->cpp[0] * 8 * 8); in radeon_crtc_do_set_base()
504 int byteshift = target_fb->format->cpp[0] * 8 >> 4; in radeon_crtc_do_set_base()
505 int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11; in radeon_crtc_do_set_base()
511 switch (target_fb->format->cpp[0] * 8) { in radeon_crtc_do_set_base()
533 if (radeon_crtc->crtc_id == 1) in radeon_crtc_do_set_base()
546 WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr); in radeon_crtc_do_set_base()
549 if (radeon_crtc->crtc_id) in radeon_crtc_do_set_base()
554 WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl); in radeon_crtc_do_set_base()
555 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset); in radeon_crtc_do_set_base()
556 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch); in radeon_crtc_do_set_base()
558 if (!atomic && fb && fb != crtc->primary->fb) { in radeon_crtc_do_set_base()
559 rbo = gem_to_radeon_bo(fb->obj[0]); in radeon_crtc_do_set_base()
575 struct drm_device *dev = crtc->dev; in radeon_set_crtc_timing()
576 struct radeon_device *rdev = dev->dev_private; in radeon_set_crtc_timing()
578 const struct drm_framebuffer *fb = crtc->primary->fb; in radeon_set_crtc_timing()
591 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in radeon_set_crtc_timing()
592 if (encoder->crtc == crtc) { in radeon_set_crtc_timing()
594 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { in radeon_set_crtc_timing()
596 DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id); in radeon_set_crtc_timing()
602 switch (fb->format->cpp[0] * 8) { in radeon_set_crtc_timing()
622 crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff) in radeon_set_crtc_timing()
623 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); in radeon_set_crtc_timing()
625 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; in radeon_set_crtc_timing()
628 hsync_start = mode->crtc_hsync_start - 8; in radeon_set_crtc_timing()
632 | ((mode->flags & DRM_MODE_FLAG_NHSYNC) in radeon_set_crtc_timing()
637 crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff) in radeon_set_crtc_timing()
638 | ((mode->crtc_vdisplay - 1) << 16)); in radeon_set_crtc_timing()
640 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; in radeon_set_crtc_timing()
644 crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff) in radeon_set_crtc_timing()
646 | ((mode->flags & DRM_MODE_FLAG_NVSYNC) in radeon_set_crtc_timing()
650 if (radeon_crtc->crtc_id) { in radeon_set_crtc_timing()
654 /* if TV DAC is enabled for another crtc and keep it enabled */ in radeon_set_crtc_timing()
661 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN) in radeon_set_crtc_timing()
664 | ((mode->flags & DRM_MODE_FLAG_CSYNC) in radeon_set_crtc_timing()
667 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) in radeon_set_crtc_timing()
671 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */ in radeon_set_crtc_timing()
672 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480)) in radeon_set_crtc_timing()
692 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN) in radeon_set_crtc_timing()
695 | ((mode->flags & DRM_MODE_FLAG_CSYNC) in radeon_set_crtc_timing()
698 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) in radeon_set_crtc_timing()
702 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */ in radeon_set_crtc_timing()
703 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480)) in radeon_set_crtc_timing()
725 WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp); in radeon_set_crtc_timing()
726 WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid); in radeon_set_crtc_timing()
727 WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp); in radeon_set_crtc_timing()
728 WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid); in radeon_set_crtc_timing()
735 struct drm_device *dev = crtc->dev; in radeon_set_pll()
736 struct radeon_device *rdev = dev->dev_private; in radeon_set_pll()
746 /* PLL registers */ in radeon_set_pll()
751 struct radeon_pll *pll; in radeon_set_pll() local
759 * Manual P/N RRG-G04100-C Rev. 0.04), page in radeon_set_pll()
760 * 3-17 (PLL_DIV_[3:0]). in radeon_set_pll()
773 if (radeon_crtc->crtc_id) in radeon_set_pll()
774 pll = &rdev->clock.p2pll; in radeon_set_pll()
776 pll = &rdev->clock.p1pll; in radeon_set_pll()
778 pll->flags = RADEON_PLL_LEGACY; in radeon_set_pll()
780 if (mode->clock > 200000) /* range limits??? */ in radeon_set_pll()
781 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; in radeon_set_pll()
783 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; in radeon_set_pll()
785 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in radeon_set_pll()
786 if (encoder->crtc == crtc) { in radeon_set_pll()
789 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { in radeon_set_pll()
794 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) in radeon_set_pll()
795 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; in radeon_set_pll()
796 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) { in radeon_set_pll()
797 if (!rdev->is_atom_bios) { in radeon_set_pll()
799 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; in radeon_set_pll()
801 if (lvds->use_bios_dividers) { in radeon_set_pll()
802 pll_ref_div = lvds->panel_ref_divider; in radeon_set_pll()
803 pll_fb_post_div = (lvds->panel_fb_divider | in radeon_set_pll()
804 (lvds->panel_post_divider << 16)); in radeon_set_pll()
810 pll->flags |= RADEON_PLL_USE_REF_DIV; in radeon_set_pll()
818 radeon_compute_pll_legacy(pll, mode->clock, in radeon_set_pll()
822 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { in radeon_set_pll()
823 if (post_div->divider == post_divider) in radeon_set_pll()
827 if (!post_div->divider) in radeon_set_pll()
839 if (info->MacModel == RADEON_MAC_IBOOK) in radeon_set_pll()
843 pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16)); in radeon_set_pll()
845 htotal_cntl = mode->htotal & 0x7; in radeon_set_pll()
849 pll_gain = radeon_compute_pll_gain(pll->reference_freq, in radeon_set_pll()
853 if (radeon_crtc->crtc_id) { in radeon_set_pll()
927 if (rdev->flags & RADEON_IS_MOBILITY) { in radeon_set_pll()
929 This appears to related to the PLL divider registers (fail to lock?). in radeon_set_pll()
931 In this case we really don't need to fiddle with PLL registers. in radeon_set_pll()
964 (rdev->family == CHIP_RS300) || in radeon_set_pll()
965 (rdev->family == CHIP_RS400) || in radeon_set_pll()
966 (rdev->family == CHIP_RS480)) { in radeon_set_pll()
1047 if (radeon_crtc->crtc_id == 0) { in radeon_crtc_mode_set()
1050 if (radeon_crtc->rmx_type != RMX_OFF) { in radeon_crtc_mode_set()
1063 struct drm_device *dev = crtc->dev; in radeon_crtc_prepare()
1070 list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) in radeon_crtc_prepare()
1076 struct drm_device *dev = crtc->dev; in radeon_crtc_commit()
1082 list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) { in radeon_crtc_commit()
1083 if (crtci->enabled) in radeon_crtc_commit()
1091 if (crtc->primary->fb) { in radeon_crtc_disable()
1095 rbo = gem_to_radeon_bo(crtc->primary->fb->obj[0]); in radeon_crtc_disable()
1122 if (radeon_crtc->crtc_id == 1) in radeon_legacy_init_crtc()
1123 radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP; in radeon_legacy_init_crtc()
1124 drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs); in radeon_legacy_init_crtc()