clk/at91/sam9x60.c

1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
6 #include <dt-bindings/clock/at91.h>
29 /* Fractional PLL core output range. */
89 	 * ddrck feeds DDR controller and is enabled by bootloader thus we need
90 	 * to keep it enabled in case there is no Linux consumer for it.
149 	 * mpddr_clk feeds DDR controller and is enabled by bootloader thus we
150 	 * need to keep it enabled in case there is no Linux consumer for it.
196 	i = of_property_match_string(np, "clock-names", "td_slck");  in sam9x60_pmc_setup()
202 	i = of_property_match_string(np, "clock-names", "md_slck");  in sam9x60_pmc_setup()
208 	i = of_property_match_string(np, "clock-names", "main_xtal");  in sam9x60_pmc_setup()
240 	sam9x60_pmc->chws[PMC_MAIN] = hw;  in sam9x60_pmc_setup()
243 					   "mainck", sam9x60_pmc->chws[PMC_MAIN],  in sam9x60_pmc_setup()
266 	sam9x60_pmc->chws[PMC_PLLACK] = hw;  in sam9x60_pmc_setup()
284 	sam9x60_pmc->chws[PMC_UTMI] = hw;  in sam9x60_pmc_setup()
302 	sam9x60_pmc->chws[PMC_MCK] = hw;  in sam9x60_pmc_setup()
329 		sam9x60_pmc->pchws[i] = hw;  in sam9x60_pmc_setup()
340 		sam9x60_pmc->shws[sam9x60_systemck[i].id] = hw;  in sam9x60_pmc_setup()
354 		sam9x60_pmc->phws[sam9x60_periphck[i].id] = hw;  in sam9x60_pmc_setup()
367 		sam9x60_pmc->ghws[sam9x60_gck[i].id] = hw;  in sam9x60_pmc_setup()
378 CLK_OF_DECLARE(sam9x60_pmc, "microchip,sam9x60-pmc", sam9x60_pmc_setup);