1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/clk-provider.h>
20  * Maximum input clock to the PLL before we divide it down by 2
129 	{ .name = "clk-s-c0-fs0-ch0",	},
130 	{ .name = "clk-s-c0-fs0-ch1",	},
131 	{ .name = "clk-s-c0-fs0-ch2",	},
132 	{ .name = "clk-s-c0-fs0-ch3",	},
186 	{ .name = "clk-s-d0-fs0-ch0",	},
187 	{ .name = "clk-s-d0-fs0-ch1",	},
188 	{ .name = "clk-s-d0-fs0-ch2",	},
189 	{ .name = "clk-s-d0-fs0-ch3",	},
198 	{ .name = "clk-s-d2-fs0-ch0",	},
199 	{ .name = "clk-s-d2-fs0-ch1",	},
200 	{ .name = "clk-s-d2-fs0-ch2",	},
201 	{ .name = "clk-s-d2-fs0-ch3",	},
210 	{ .name = "clk-s-d3-fs0-ch0",	},
211 	{ .name = "clk-s-d3-fs0-ch1",	},
212 	{ .name = "clk-s-d3-fs0-ch2",	},
213 	{ .name = "clk-s-d3-fs0-ch3",	},
225  * prepare - clk_(un)prepare only ensures parent is (un)prepared
226  * enable - clk_enable and clk_disable are functional & control the Fsyn
227  * rate - inherits rate from parent. set_rate/round_rate/recalc_rate
228  * parent - fixed parent.  No clk_set_parent support
232  * struct st_clk_quadfs_pll - A pll which outputs a fixed multiplier of
236  * @hw: handle between common and hardware-specific interfaces.
254 	struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw);  in quadfs_pll_enable()  local
257 	if (pll->lock)  in quadfs_pll_enable()
258 		spin_lock_irqsave(pll->lock, flags);  in quadfs_pll_enable()
263 	if (pll->data->reset_present)  in quadfs_pll_enable()
264 		CLKGEN_WRITE(pll, nreset, 1);  in quadfs_pll_enable()
269 	if (pll->data->bwfilter_present)  in quadfs_pll_enable()
270 		CLKGEN_WRITE(pll, ref_bw, PLL_BW_GOODREF);  in quadfs_pll_enable()
273 	CLKGEN_WRITE(pll, ndiv, pll->ndiv);  in quadfs_pll_enable()
276 	 * Power up the PLL  in quadfs_pll_enable()
278 	CLKGEN_WRITE(pll, npda, !pll->data->powerup_polarity);  in quadfs_pll_enable()
280 	if (pll->lock)  in quadfs_pll_enable()
281 		spin_unlock_irqrestore(pll->lock, flags);  in quadfs_pll_enable()
283 	if (pll->data->lockstatus_present)  in quadfs_pll_enable()
284 		while (!CLKGEN_READ(pll, lock_status)) {  in quadfs_pll_enable()
286 				return -ETIMEDOUT;  in quadfs_pll_enable()
295 	struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw);  in quadfs_pll_disable()  local
298 	if (pll->lock)  in quadfs_pll_disable()
299 		spin_lock_irqsave(pll->lock, flags);  in quadfs_pll_disable()
302 	 * Powerdown the PLL and then put block into soft reset if we have  in quadfs_pll_disable()
305 	CLKGEN_WRITE(pll, npda, pll->data->powerup_polarity);  in quadfs_pll_disable()
307 	if (pll->data->reset_present)  in quadfs_pll_disable()
308 		CLKGEN_WRITE(pll, nreset, 0);  in quadfs_pll_disable()
310 	if (pll->lock)  in quadfs_pll_disable()
311 		spin_unlock_irqrestore(pll->lock, flags);  in quadfs_pll_disable()
316 	struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw);  in quadfs_pll_is_enabled()  local
317 	u32 npda = CLKGEN_READ(pll, npda);  in quadfs_pll_is_enabled()
319 	return pll->data->powerup_polarity ? !npda : !!npda;  in quadfs_pll_is_enabled()
325 	unsigned long nd = fs->ndiv + 16; /* ndiv value */  in clk_fs660c32_vco_get_rate()
335 	struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw);  in quadfs_pll_fs660c32_recalc_rate()  local
339 	params.ndiv = CLKGEN_READ(pll, ndiv);  in quadfs_pll_fs660c32_recalc_rate()
344 	pll->ndiv = params.ndiv;  in quadfs_pll_fs660c32_recalc_rate()
360 		return -EINVAL;  in clk_fs660c32_vco_get_params()
365 		return -EINVAL;  in clk_fs660c32_vco_get_params()
373 	fs->ndiv = n - 16; /* Converting formula value to reg value */  in clk_fs660c32_vco_get_params()
399 	struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw);  in quadfs_pll_fs660c32_set_rate()  local
406 		return -EINVAL;  in quadfs_pll_fs660c32_set_rate()
419 		return -EINVAL;  in quadfs_pll_fs660c32_set_rate()
421 	pll->ndiv = params.ndiv;  in quadfs_pll_fs660c32_set_rate()
423 	if (pll->lock)  in quadfs_pll_fs660c32_set_rate()
424 		spin_lock_irqsave(pll->lock, flags);  in quadfs_pll_fs660c32_set_rate()
426 	CLKGEN_WRITE(pll, ndiv, pll->ndiv);  in quadfs_pll_fs660c32_set_rate()
428 	if (pll->lock)  in quadfs_pll_fs660c32_set_rate()
429 		spin_unlock_irqrestore(pll->lock, flags);  in quadfs_pll_fs660c32_set_rate()
448 	struct st_clk_quadfs_pll *pll;  in st_clk_register_quadfs_pll()  local
456 		return ERR_PTR(-EINVAL);  in st_clk_register_quadfs_pll()
458 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);  in st_clk_register_quadfs_pll()
459 	if (!pll)  in st_clk_register_quadfs_pll()
460 		return ERR_PTR(-ENOMEM);  in st_clk_register_quadfs_pll()
463 	init.ops = quadfs->pll_ops;  in st_clk_register_quadfs_pll()
468 	pll->data = quadfs;  in st_clk_register_quadfs_pll()
469 	pll->regs_base = reg;  in st_clk_register_quadfs_pll()
470 	pll->lock = lock;  in st_clk_register_quadfs_pll()
471 	pll->hw.init = &init;  in st_clk_register_quadfs_pll()
473 	clk = clk_register(NULL, &pll->hw);  in st_clk_register_quadfs_pll()
476 		kfree(pll);  in st_clk_register_quadfs_pll()
485  * prepare - clk_(un)prepare only ensures parent is (un)prepared
486  * enable - clk_enable and clk_disable are functional
487  * rate - set rate is functional
488  * parent - fixed parent.  No clk_set_parent support
492  * struct st_clk_quadfs_fsynth - One clock output from a four channel digital
495  * @hw: handle between common and hardware-specific interfaces
518 	 *     enabled.
539 	CLKGEN_WRITE(fs, en[fs->chan], 1);  in quadfs_fsynth_program_enable()
540 	CLKGEN_WRITE(fs, en[fs->chan], 0);  in quadfs_fsynth_program_enable()
552 	CLKGEN_WRITE(fs, en[fs->chan], 0);  in quadfs_fsynth_program_rate()
554 	CLKGEN_WRITE(fs, mdiv[fs->chan], fs->md);  in quadfs_fsynth_program_rate()
555 	CLKGEN_WRITE(fs, pe[fs->chan], fs->pe);  in quadfs_fsynth_program_rate()
556 	CLKGEN_WRITE(fs, sdiv[fs->chan], fs->sdiv);  in quadfs_fsynth_program_rate()
558 	if (fs->lock)  in quadfs_fsynth_program_rate()
559 		spin_lock_irqsave(fs->lock, flags);  in quadfs_fsynth_program_rate()
561 	if (fs->data->nsdiv_present)  in quadfs_fsynth_program_rate()
562 		CLKGEN_WRITE(fs, nsdiv[fs->chan], fs->nsdiv);  in quadfs_fsynth_program_rate()
564 	if (fs->lock)  in quadfs_fsynth_program_rate()
565 		spin_unlock_irqrestore(fs->lock, flags);  in quadfs_fsynth_program_rate()
577 	if (fs->lock)  in quadfs_fsynth_enable()
578 		spin_lock_irqsave(fs->lock, flags);  in quadfs_fsynth_enable()
580 	CLKGEN_WRITE(fs, nsb[fs->chan], !fs->data->standby_polarity);  in quadfs_fsynth_enable()
582 	if (fs->data->nrst_present)  in quadfs_fsynth_enable()
583 		CLKGEN_WRITE(fs, nrst[fs->chan], 0);  in quadfs_fsynth_enable()
585 	if (fs->lock)  in quadfs_fsynth_enable()
586 		spin_unlock_irqrestore(fs->lock, flags);  in quadfs_fsynth_enable()
600 	if (fs->lock)  in quadfs_fsynth_disable()
601 		spin_lock_irqsave(fs->lock, flags);  in quadfs_fsynth_disable()
603 	CLKGEN_WRITE(fs, nsb[fs->chan], fs->data->standby_polarity);  in quadfs_fsynth_disable()
605 	if (fs->lock)  in quadfs_fsynth_disable()
606 		spin_unlock_irqrestore(fs->lock, flags);  in quadfs_fsynth_disable()
612 	u32 nsb = CLKGEN_READ(fs, nsb[fs->chan]);  in quadfs_fsynth_is_enabled()
617 	return fs->data->standby_polarity ? !nsb : !!nsb;  in quadfs_fsynth_is_enabled()
625 	unsigned long s = (1 << fs->sdiv);  in clk_fs660c32_dig_get_rate()
637 	ns = (fs->nsdiv == 1) ? 1 : 3;  in clk_fs660c32_dig_get_rate()
639 	res = (P20 * (32 + fs->mdiv) + 32 * fs->pe) * s * ns;  in clk_fs660c32_dig_get_rate()
656 	*p = (uint64_t)input * P20 - (32LL  + (uint64_t)m) * val * (P20 / 32LL);  in clk_fs660c32_get_pe()
670 	new_deviation = abs(output - new_freq);  in clk_fs660c32_get_pe()
673 		fs->mdiv = m;  in clk_fs660c32_get_pe()
674 		fs->pe = (unsigned long)*p;  in clk_fs660c32_get_pe()
675 		fs->sdiv = si;  in clk_fs660c32_get_pe()
676 		fs->nsdiv = 1;  in clk_fs660c32_get_pe()
715 		return -1;  in clk_fs660c32_dig_get_params()
717 	/* pe fine tuning if deviation not 0: +/- 2 around computed pe value */  in clk_fs660c32_dig_get_params()
719 		fs_tmp.mdiv = fs->mdiv;  in clk_fs660c32_dig_get_params()
720 		fs_tmp.sdiv = fs->sdiv;  in clk_fs660c32_dig_get_params()
721 		fs_tmp.nsdiv = fs->nsdiv;  in clk_fs660c32_dig_get_params()
723 		if (fs->pe > 2)  in clk_fs660c32_dig_get_params()
724 			p2 = fs->pe - 2;  in clk_fs660c32_dig_get_params()
728 		for (; p2 < 32768ll && (p2 <= (fs->pe + 2)); p2++) {  in clk_fs660c32_dig_get_params()
733 			new_deviation = abs(output - new_freq);  in clk_fs660c32_dig_get_params()
737 				fs->pe = (unsigned long)p2;  in clk_fs660c32_dig_get_params()
752 	params->mdiv	= CLKGEN_READ(fs, mdiv[fs->chan]);  in quadfs_fsynt_get_hw_value_for_recalc()
753 	params->pe	= CLKGEN_READ(fs, pe[fs->chan]);  in quadfs_fsynt_get_hw_value_for_recalc()
754 	params->sdiv	= CLKGEN_READ(fs, sdiv[fs->chan]);  in quadfs_fsynt_get_hw_value_for_recalc()
756 	if (fs->data->nsdiv_present)  in quadfs_fsynt_get_hw_value_for_recalc()
757 		params->nsdiv = CLKGEN_READ(fs, nsdiv[fs->chan]);  in quadfs_fsynt_get_hw_value_for_recalc()
759 		params->nsdiv = 1;  in quadfs_fsynt_get_hw_value_for_recalc()
764 	if (!params->mdiv && !params->pe && !params->sdiv)  in quadfs_fsynt_get_hw_value_for_recalc()
767 	fs->md = params->mdiv;  in quadfs_fsynt_get_hw_value_for_recalc()
768 	fs->pe = params->pe;  in quadfs_fsynt_get_hw_value_for_recalc()
769 	fs->sdiv = params->sdiv;  in quadfs_fsynt_get_hw_value_for_recalc()
770 	fs->nsdiv = params->nsdiv;  in quadfs_fsynt_get_hw_value_for_recalc()
784 	clk_fs_get_rate = fs->data->get_rate;  in quadfs_find_best_rate()
785 	clk_fs_get_params = fs->data->get_params;  in quadfs_find_best_rate()
802 	clk_fs_get_rate = fs->data->get_rate;  in quadfs_recalc_rate()
836 	fs->md = params->mdiv;  in quadfs_program_and_enable()
837 	fs->pe = params->pe;  in quadfs_program_and_enable()
838 	fs->sdiv = params->sdiv;  in quadfs_program_and_enable()
839 	fs->nsdiv = params->nsdiv;  in quadfs_program_and_enable()
843 	 * the parent entity containing it is enabled.  in quadfs_program_and_enable()
857 		return -EINVAL;  in quadfs_set_rate()
863 		return -EINVAL;  in quadfs_set_rate()
894 		return ERR_PTR(-EINVAL);  in st_clk_register_quadfs_fsynth()
898 		return ERR_PTR(-ENOMEM);  in st_clk_register_quadfs_fsynth()
906 	fs->data = quadfs;  in st_clk_register_quadfs_fsynth()
907 	fs->regs_base = reg;  in st_clk_register_quadfs_fsynth()
908 	fs->chan = chan;  in st_clk_register_quadfs_fsynth()
909 	fs->lock = lock;  in st_clk_register_quadfs_fsynth()
910 	fs->hw.init = &init;  in st_clk_register_quadfs_fsynth()
912 	clk = clk_register(NULL, &fs->hw);  in st_clk_register_quadfs_fsynth()
932 	clk_data->clk_num = QUADFS_MAX_CHAN;  in st_of_create_quadfs_fsynths()
933 	clk_data->clks = kcalloc(QUADFS_MAX_CHAN, sizeof(struct clk *),  in st_of_create_quadfs_fsynths()
936 	if (!clk_data->clks) {  in st_of_create_quadfs_fsynths()
946 		if (quadfs->outputs) {  in st_of_create_quadfs_fsynths()
947 			clk_name = quadfs->outputs[fschan].name;  in st_of_create_quadfs_fsynths()
948 			flags = quadfs->outputs[fschan].flags;  in st_of_create_quadfs_fsynths()
951 							"clock-output-names",  in st_of_create_quadfs_fsynths()
964 						    quadfs->data, reg, fschan,  in st_of_create_quadfs_fsynths()
972 			clk_data->clks[fschan] = clk;  in st_of_create_quadfs_fsynths()
993 	 * First check for reg property within the node to keep backward  in st_of_quadfs_setup()
1011 	pll_name = kasprintf(GFP_KERNEL, "%pOFn.pll", np);  in st_of_quadfs_setup()
1021 	clk = st_clk_register_quadfs_pll(pll_name, clk_parent_name, datac->data,  in st_of_quadfs_setup()
1035 	kfree(pll_name); /* No longer need local copy of the PLL name */  in st_of_quadfs_setup()
1043 CLK_OF_DECLARE(quadfs660C, "st,quadfs-pll", st_of_quadfs660C_setup);
1057 CLK_OF_DECLARE(quadfs660D0, "st,quadfs-d0", st_of_quadfs660D0_setup);
1064 CLK_OF_DECLARE(quadfs660D2, "st,quadfs-d2", st_of_quadfs660D2_setup);
1071 CLK_OF_DECLARE(quadfs660D3, "st,quadfs-d3", st_of_quadfs660D3_setup);