Lines Matching +full:keep +full:- +full:pll +full:- +full:enabled
1 // SPDX-License-Identifier: MIT
196 * the range value for them is (actual_value - 2).
308 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
309 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
313 * divided-down version of it.
318 clock->m = clock->m2 + 2; in pnv_calc_dpll_params()
319 clock->p = clock->p1 * clock->p2; in pnv_calc_dpll_params()
321 clock->vco = clock->n == 0 ? 0 : in pnv_calc_dpll_params()
322 DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); in pnv_calc_dpll_params()
323 clock->dot = clock->p == 0 ? 0 : in pnv_calc_dpll_params()
324 DIV_ROUND_CLOSEST(clock->vco, clock->p); in pnv_calc_dpll_params()
326 return clock->dot; in pnv_calc_dpll_params()
331 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m()
336 clock->m = i9xx_dpll_compute_m(clock); in i9xx_calc_dpll_params()
337 clock->p = clock->p1 * clock->p2; in i9xx_calc_dpll_params()
339 clock->vco = clock->n + 2 == 0 ? 0 : in i9xx_calc_dpll_params()
340 DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); in i9xx_calc_dpll_params()
341 clock->dot = clock->p == 0 ? 0 : in i9xx_calc_dpll_params()
342 DIV_ROUND_CLOSEST(clock->vco, clock->p); in i9xx_calc_dpll_params()
344 return clock->dot; in i9xx_calc_dpll_params()
349 clock->m = clock->m1 * clock->m2; in vlv_calc_dpll_params()
350 clock->p = clock->p1 * clock->p2 * 5; in vlv_calc_dpll_params()
352 clock->vco = clock->n == 0 ? 0 : in vlv_calc_dpll_params()
353 DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); in vlv_calc_dpll_params()
354 clock->dot = clock->p == 0 ? 0 : in vlv_calc_dpll_params()
355 DIV_ROUND_CLOSEST(clock->vco, clock->p); in vlv_calc_dpll_params()
357 return clock->dot; in vlv_calc_dpll_params()
362 clock->m = clock->m1 * clock->m2; in chv_calc_dpll_params()
363 clock->p = clock->p1 * clock->p2 * 5; in chv_calc_dpll_params()
365 clock->vco = clock->n == 0 ? 0 : in chv_calc_dpll_params()
366 DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), clock->n << 22); in chv_calc_dpll_params()
367 clock->dot = clock->p == 0 ? 0 : in chv_calc_dpll_params()
368 DIV_ROUND_CLOSEST(clock->vco, clock->p); in chv_calc_dpll_params()
370 return clock->dot; in chv_calc_dpll_params()
375 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in i9xx_pll_refclk()
376 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in i9xx_pll_refclk()
378 if ((hw_state->dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) in i9xx_pll_refclk()
379 return i915->display.vbt.lvds_ssc_freq; in i9xx_pll_refclk()
391 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_dpll_get_hw_state()
392 struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx; in i9xx_dpll_get_hw_state()
398 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) in i9xx_dpll_get_hw_state()
399 tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe]; in i9xx_dpll_get_hw_state()
402 DPLL_MD(dev_priv, crtc->pipe)); in i9xx_dpll_get_hw_state()
404 hw_state->dpll_md = tmp; in i9xx_dpll_get_hw_state()
407 hw_state->dpll = intel_de_read(dev_priv, DPLL(dev_priv, crtc->pipe)); in i9xx_dpll_get_hw_state()
410 hw_state->fp0 = intel_de_read(dev_priv, FP0(crtc->pipe)); in i9xx_dpll_get_hw_state()
411 hw_state->fp1 = intel_de_read(dev_priv, FP1(crtc->pipe)); in i9xx_dpll_get_hw_state()
413 /* Mask out read-only status bits. */ in i9xx_dpll_get_hw_state()
414 hw_state->dpll &= ~(DPLL_LOCK_VLV | in i9xx_dpll_get_hw_state()
423 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_crtc_clock_get()
424 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_crtc_clock_get()
425 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in i9xx_crtc_clock_get()
426 u32 dpll = hw_state->dpll; in i9xx_crtc_clock_get()
433 fp = hw_state->fp0; in i9xx_crtc_clock_get()
435 fp = hw_state->fp1; in i9xx_crtc_clock_get()
439 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; in i9xx_crtc_clock_get()
464 drm_dbg_kms(&dev_priv->drm, in i9xx_crtc_clock_get()
479 lvds_pipe == crtc->pipe) { in i9xx_crtc_clock_get()
510 crtc_state->port_clock = port_clock; in i9xx_crtc_clock_get()
515 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_crtc_clock_get()
516 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in vlv_crtc_clock_get()
517 enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe); in vlv_crtc_clock_get()
518 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); in vlv_crtc_clock_get()
519 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in vlv_crtc_clock_get()
525 if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0) in vlv_crtc_clock_get()
538 crtc_state->port_clock = vlv_calc_dpll_params(refclk, &clock); in vlv_crtc_clock_get()
543 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in chv_crtc_clock_get()
544 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in chv_crtc_clock_get()
545 enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe); in chv_crtc_clock_get()
546 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); in chv_crtc_clock_get()
547 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in chv_crtc_clock_get()
553 if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0) in chv_crtc_clock_get()
572 crtc_state->port_clock = chv_calc_dpll_params(refclk, &clock); in chv_crtc_clock_get()
583 if (clock->n < limit->n.min || limit->n.max < clock->n) in intel_pll_is_valid()
585 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) in intel_pll_is_valid()
587 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) in intel_pll_is_valid()
589 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) in intel_pll_is_valid()
593 if (clock->m1 <= clock->m2) in intel_pll_is_valid()
597 if (clock->p < limit->p.min || limit->p.max < clock->p) in intel_pll_is_valid()
599 if (clock->m < limit->m.min || limit->m.max < clock->m) in intel_pll_is_valid()
603 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) in intel_pll_is_valid()
608 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) in intel_pll_is_valid()
619 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in i9xx_select_p2_div()
623 * For LVDS just rely on its current settings for dual-channel. in i9xx_select_p2_div()
628 return limit->p2.p2_fast; in i9xx_select_p2_div()
630 return limit->p2.p2_slow; in i9xx_select_p2_div()
632 if (target < limit->p2.dot_limit) in i9xx_select_p2_div()
633 return limit->p2.p2_slow; in i9xx_select_p2_div()
635 return limit->p2.p2_fast; in i9xx_select_p2_div()
655 struct drm_device *dev = crtc_state->uapi.crtc->dev; in i9xx_find_best_dpll()
663 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; in i9xx_find_best_dpll()
665 for (clock.m2 = limit->m2.min; in i9xx_find_best_dpll()
666 clock.m2 <= limit->m2.max; clock.m2++) { in i9xx_find_best_dpll()
669 for (clock.n = limit->n.min; in i9xx_find_best_dpll()
670 clock.n <= limit->n.max; clock.n++) { in i9xx_find_best_dpll()
671 for (clock.p1 = limit->p1.min; in i9xx_find_best_dpll()
672 clock.p1 <= limit->p1.max; clock.p1++) { in i9xx_find_best_dpll()
681 clock.p != match_clock->p) in i9xx_find_best_dpll()
684 this_err = abs(clock.dot - target); in i9xx_find_best_dpll()
713 struct drm_device *dev = crtc_state->uapi.crtc->dev; in pnv_find_best_dpll()
721 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; in pnv_find_best_dpll()
723 for (clock.m2 = limit->m2.min; in pnv_find_best_dpll()
724 clock.m2 <= limit->m2.max; clock.m2++) { in pnv_find_best_dpll()
725 for (clock.n = limit->n.min; in pnv_find_best_dpll()
726 clock.n <= limit->n.max; clock.n++) { in pnv_find_best_dpll()
727 for (clock.p1 = limit->p1.min; in pnv_find_best_dpll()
728 clock.p1 <= limit->p1.max; clock.p1++) { in pnv_find_best_dpll()
737 clock.p != match_clock->p) in pnv_find_best_dpll()
740 this_err = abs(clock.dot - target); in pnv_find_best_dpll()
769 struct drm_device *dev = crtc_state->uapi.crtc->dev; in g4x_find_best_dpll()
780 max_n = limit->n.max; in g4x_find_best_dpll()
782 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { in g4x_find_best_dpll()
784 for (clock.m1 = limit->m1.max; in g4x_find_best_dpll()
785 clock.m1 >= limit->m1.min; clock.m1--) { in g4x_find_best_dpll()
786 for (clock.m2 = limit->m2.max; in g4x_find_best_dpll()
787 clock.m2 >= limit->m2.min; clock.m2--) { in g4x_find_best_dpll()
788 for (clock.p1 = limit->p1.max; in g4x_find_best_dpll()
789 clock.p1 >= limit->p1.min; clock.p1--) { in g4x_find_best_dpll()
798 this_err = abs(clock.dot - target); in g4x_find_best_dpll()
813 * Check if the calculated PLL configuration is more optimal compared to the
829 return calculated_clock->p > best_clock->p; in vlv_PLL_is_optimal()
836 abs(target_freq - calculated_clock->dot), in vlv_PLL_is_optimal()
843 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { in vlv_PLL_is_optimal()
863 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_find_best_dpll()
864 struct drm_device *dev = crtc->base.dev; in vlv_find_best_dpll()
868 int max_n = min(limit->n.max, refclk / 19200); in vlv_find_best_dpll()
874 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { in vlv_find_best_dpll()
875 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { in vlv_find_best_dpll()
876 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; in vlv_find_best_dpll()
877 clock.p2 -= clock.p2 > 10 ? 2 : 1) { in vlv_find_best_dpll()
880 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { in vlv_find_best_dpll()
921 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in chv_find_best_dpll()
922 struct drm_device *dev = crtc->base.dev; in chv_find_best_dpll()
939 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { in chv_find_best_dpll()
940 for (clock.p2 = limit->p2.p2_fast; in chv_find_best_dpll()
941 clock.p2 >= limit->p2.p2_slow; in chv_find_best_dpll()
942 clock.p2 -= clock.p2 > 10 ? 2 : 1) { in chv_find_best_dpll()
980 crtc_state->port_clock, refclk, in bxt_find_best_dpll()
986 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; in i9xx_dpll_compute_fp()
991 return (1 << dpll->n) << 16 | dpll->m2; in pnv_dpll_compute_fp()
996 return (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; in i965_dpll_md()
1003 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_dpll()
1004 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_dpll()
1016 dpll |= (crtc_state->pixel_multiplier - 1) in i9xx_dpll()
1029 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_dpll()
1030 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in i9xx_dpll()
1032 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; in i9xx_dpll()
1033 WARN_ON(reduced_clock->p1 != clock->p1); in i9xx_dpll()
1035 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_dpll()
1036 WARN_ON(reduced_clock->p1 != clock->p1); in i9xx_dpll()
1039 switch (clock->p2) { in i9xx_dpll()
1053 WARN_ON(reduced_clock->p2 != clock->p2); in i9xx_dpll()
1058 if (crtc_state->sdvo_tv_clock) in i9xx_dpll()
1073 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_compute_dpll()
1074 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_compute_dpll()
1075 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in i9xx_compute_dpll()
1078 hw_state->fp0 = pnv_dpll_compute_fp(clock); in i9xx_compute_dpll()
1079 hw_state->fp1 = pnv_dpll_compute_fp(reduced_clock); in i9xx_compute_dpll()
1081 hw_state->fp0 = i9xx_dpll_compute_fp(clock); in i9xx_compute_dpll()
1082 hw_state->fp1 = i9xx_dpll_compute_fp(reduced_clock); in i9xx_compute_dpll()
1085 hw_state->dpll = i9xx_dpll(crtc_state, clock, reduced_clock); in i9xx_compute_dpll()
1088 hw_state->dpll_md = i965_dpll_md(crtc_state); in i9xx_compute_dpll()
1095 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i8xx_dpll()
1096 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i8xx_dpll()
1102 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_dpll()
1104 if (clock->p1 == 2) in i8xx_dpll()
1107 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_dpll()
1108 if (clock->p2 == 4) in i8xx_dpll()
1111 WARN_ON(reduced_clock->p1 != clock->p1); in i8xx_dpll()
1112 WARN_ON(reduced_clock->p2 != clock->p2); in i8xx_dpll()
1120 * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)." in i8xx_dpll()
1122 * For simplicity We simply keep both bits always enabled in in i8xx_dpll()
1143 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in i8xx_compute_dpll()
1145 hw_state->fp0 = i9xx_dpll_compute_fp(clock); in i8xx_compute_dpll()
1146 hw_state->fp1 = i9xx_dpll_compute_fp(reduced_clock); in i8xx_compute_dpll()
1148 hw_state->dpll = i8xx_dpll(crtc_state, clock, reduced_clock); in i8xx_compute_dpll()
1154 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in hsw_crtc_compute_clock()
1174 if (!crtc_state->has_pch_encoder) in hsw_crtc_compute_clock()
1175 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in hsw_crtc_compute_clock()
1183 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in hsw_crtc_get_shared_dpll()
1209 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in dg2_crtc_compute_clock()
1228 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); in mtl_crtc_compute_clock()
1230 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in mtl_crtc_compute_clock()
1237 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ilk_fb_cb_factor()
1238 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in ilk_fb_cb_factor()
1241 ((intel_panel_use_ssc(i915) && i915->display.vbt.lvds_ssc_freq == 100000) || in ilk_fb_cb_factor()
1245 if (crtc_state->sdvo_tv_clock) in ilk_fb_cb_factor()
1253 return dpll->m < factor * dpll->n; in ilk_needs_fb_cb_tune()
1271 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ilk_dpll()
1272 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_dpll()
1282 dpll |= (crtc_state->pixel_multiplier - 1) in ilk_dpll()
1304 * this on ILK at all since it has a fixed DPLL<->pipe mapping. in ilk_dpll()
1311 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in ilk_dpll()
1313 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in ilk_dpll()
1315 switch (clock->p2) { in ilk_dpll()
1329 WARN_ON(reduced_clock->p2 != clock->p2); in ilk_dpll()
1344 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in ilk_compute_dpll()
1347 hw_state->fp0 = ilk_dpll_compute_fp(clock, factor); in ilk_compute_dpll()
1348 hw_state->fp1 = ilk_dpll_compute_fp(reduced_clock, factor); in ilk_compute_dpll()
1350 hw_state->dpll = ilk_dpll(crtc_state, clock, reduced_clock); in ilk_compute_dpll()
1356 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in ilk_crtc_compute_clock()
1363 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ in ilk_crtc_compute_clock()
1364 if (!crtc_state->has_pch_encoder) in ilk_crtc_compute_clock()
1369 drm_dbg_kms(&dev_priv->drm, in ilk_crtc_compute_clock()
1371 dev_priv->display.vbt.lvds_ssc_freq); in ilk_crtc_compute_clock()
1372 refclk = dev_priv->display.vbt.lvds_ssc_freq; in ilk_crtc_compute_clock()
1390 if (!crtc_state->clock_set && in ilk_crtc_compute_clock()
1391 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in ilk_crtc_compute_clock()
1392 refclk, NULL, &crtc_state->dpll)) in ilk_crtc_compute_clock()
1393 return -EINVAL; in ilk_crtc_compute_clock()
1395 i9xx_calc_dpll_params(refclk, &crtc_state->dpll); in ilk_crtc_compute_clock()
1397 ilk_compute_dpll(crtc_state, &crtc_state->dpll, in ilk_crtc_compute_clock()
1398 &crtc_state->dpll); in ilk_crtc_compute_clock()
1404 crtc_state->port_clock = crtc_state->dpll.dot; in ilk_crtc_compute_clock()
1405 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in ilk_crtc_compute_clock()
1416 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ in ilk_crtc_get_shared_dpll()
1417 if (!crtc_state->has_pch_encoder) in ilk_crtc_get_shared_dpll()
1425 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_dpll()
1431 if (crtc->pipe != PIPE_A) in vlv_dpll()
1443 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in vlv_compute_dpll()
1445 hw_state->dpll = vlv_dpll(crtc_state); in vlv_compute_dpll()
1446 hw_state->dpll_md = i965_dpll_md(crtc_state); in vlv_compute_dpll()
1451 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in chv_dpll()
1457 if (crtc->pipe != PIPE_A) in chv_dpll()
1469 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in chv_compute_dpll()
1471 hw_state->dpll = chv_dpll(crtc_state); in chv_compute_dpll()
1472 hw_state->dpll_md = i965_dpll_md(crtc_state); in chv_compute_dpll()
1483 if (!crtc_state->clock_set && in chv_crtc_compute_clock()
1484 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in chv_crtc_compute_clock()
1485 refclk, NULL, &crtc_state->dpll)) in chv_crtc_compute_clock()
1486 return -EINVAL; in chv_crtc_compute_clock()
1488 chv_calc_dpll_params(refclk, &crtc_state->dpll); in chv_crtc_compute_clock()
1496 crtc_state->port_clock = crtc_state->dpll.dot; in chv_crtc_compute_clock()
1497 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in chv_crtc_compute_clock()
1510 if (!crtc_state->clock_set && in vlv_crtc_compute_clock()
1511 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in vlv_crtc_compute_clock()
1512 refclk, NULL, &crtc_state->dpll)) in vlv_crtc_compute_clock()
1513 return -EINVAL; in vlv_crtc_compute_clock()
1515 vlv_calc_dpll_params(refclk, &crtc_state->dpll); in vlv_crtc_compute_clock()
1523 crtc_state->port_clock = crtc_state->dpll.dot; in vlv_crtc_compute_clock()
1524 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in vlv_crtc_compute_clock()
1532 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in g4x_crtc_compute_clock()
1540 refclk = dev_priv->display.vbt.lvds_ssc_freq; in g4x_crtc_compute_clock()
1541 drm_dbg_kms(&dev_priv->drm, in g4x_crtc_compute_clock()
1560 if (!crtc_state->clock_set && in g4x_crtc_compute_clock()
1561 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in g4x_crtc_compute_clock()
1562 refclk, NULL, &crtc_state->dpll)) in g4x_crtc_compute_clock()
1563 return -EINVAL; in g4x_crtc_compute_clock()
1565 i9xx_calc_dpll_params(refclk, &crtc_state->dpll); in g4x_crtc_compute_clock()
1567 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in g4x_crtc_compute_clock()
1568 &crtc_state->dpll); in g4x_crtc_compute_clock()
1570 crtc_state->port_clock = crtc_state->dpll.dot; in g4x_crtc_compute_clock()
1573 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in g4x_crtc_compute_clock()
1581 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in pnv_crtc_compute_clock()
1589 refclk = dev_priv->display.vbt.lvds_ssc_freq; in pnv_crtc_compute_clock()
1590 drm_dbg_kms(&dev_priv->drm, in pnv_crtc_compute_clock()
1600 if (!crtc_state->clock_set && in pnv_crtc_compute_clock()
1601 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in pnv_crtc_compute_clock()
1602 refclk, NULL, &crtc_state->dpll)) in pnv_crtc_compute_clock()
1603 return -EINVAL; in pnv_crtc_compute_clock()
1605 pnv_calc_dpll_params(refclk, &crtc_state->dpll); in pnv_crtc_compute_clock()
1607 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in pnv_crtc_compute_clock()
1608 &crtc_state->dpll); in pnv_crtc_compute_clock()
1610 crtc_state->port_clock = crtc_state->dpll.dot; in pnv_crtc_compute_clock()
1611 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in pnv_crtc_compute_clock()
1619 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in i9xx_crtc_compute_clock()
1627 refclk = dev_priv->display.vbt.lvds_ssc_freq; in i9xx_crtc_compute_clock()
1628 drm_dbg_kms(&dev_priv->drm, in i9xx_crtc_compute_clock()
1638 if (!crtc_state->clock_set && in i9xx_crtc_compute_clock()
1639 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in i9xx_crtc_compute_clock()
1640 refclk, NULL, &crtc_state->dpll)) in i9xx_crtc_compute_clock()
1641 return -EINVAL; in i9xx_crtc_compute_clock()
1643 i9xx_calc_dpll_params(refclk, &crtc_state->dpll); in i9xx_crtc_compute_clock()
1645 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in i9xx_crtc_compute_clock()
1646 &crtc_state->dpll); in i9xx_crtc_compute_clock()
1648 crtc_state->port_clock = crtc_state->dpll.dot; in i9xx_crtc_compute_clock()
1651 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in i9xx_crtc_compute_clock()
1659 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in i8xx_crtc_compute_clock()
1667 refclk = dev_priv->display.vbt.lvds_ssc_freq; in i8xx_crtc_compute_clock()
1668 drm_dbg_kms(&dev_priv->drm, in i8xx_crtc_compute_clock()
1680 if (!crtc_state->clock_set && in i8xx_crtc_compute_clock()
1681 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in i8xx_crtc_compute_clock()
1682 refclk, NULL, &crtc_state->dpll)) in i8xx_crtc_compute_clock()
1683 return -EINVAL; in i8xx_crtc_compute_clock()
1685 i9xx_calc_dpll_params(refclk, &crtc_state->dpll); in i8xx_crtc_compute_clock()
1687 i8xx_compute_dpll(crtc_state, &crtc_state->dpll, in i8xx_crtc_compute_clock()
1688 &crtc_state->dpll); in i8xx_crtc_compute_clock()
1690 crtc_state->port_clock = crtc_state->dpll.dot; in i8xx_crtc_compute_clock()
1691 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); in i8xx_crtc_compute_clock()
1741 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_dpll_crtc_compute_clock()
1746 drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state)); in intel_dpll_crtc_compute_clock()
1748 memset(&crtc_state->dpll_hw_state, 0, in intel_dpll_crtc_compute_clock()
1749 sizeof(crtc_state->dpll_hw_state)); in intel_dpll_crtc_compute_clock()
1751 if (!crtc_state->hw.enable) in intel_dpll_crtc_compute_clock()
1754 ret = i915->display.funcs.dpll->crtc_compute_clock(state, crtc); in intel_dpll_crtc_compute_clock()
1756 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't calculate DPLL settings\n", in intel_dpll_crtc_compute_clock()
1757 crtc->base.base.id, crtc->base.name); in intel_dpll_crtc_compute_clock()
1767 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_dpll_crtc_get_shared_dpll()
1772 drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state)); in intel_dpll_crtc_get_shared_dpll()
1773 drm_WARN_ON(&i915->drm, !crtc_state->hw.enable && crtc_state->shared_dpll); in intel_dpll_crtc_get_shared_dpll()
1775 if (!crtc_state->hw.enable || crtc_state->shared_dpll) in intel_dpll_crtc_get_shared_dpll()
1778 if (!i915->display.funcs.dpll->crtc_get_shared_dpll) in intel_dpll_crtc_get_shared_dpll()
1781 ret = i915->display.funcs.dpll->crtc_get_shared_dpll(state, crtc); in intel_dpll_crtc_get_shared_dpll()
1783 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n", in intel_dpll_crtc_get_shared_dpll()
1784 crtc->base.base.id, crtc->base.name); in intel_dpll_crtc_get_shared_dpll()
1795 dev_priv->display.funcs.dpll = &mtl_dpll_funcs; in intel_dpll_init_clock_hook()
1797 dev_priv->display.funcs.dpll = &dg2_dpll_funcs; in intel_dpll_init_clock_hook()
1799 dev_priv->display.funcs.dpll = &hsw_dpll_funcs; in intel_dpll_init_clock_hook()
1801 dev_priv->display.funcs.dpll = &ilk_dpll_funcs; in intel_dpll_init_clock_hook()
1803 dev_priv->display.funcs.dpll = &chv_dpll_funcs; in intel_dpll_init_clock_hook()
1805 dev_priv->display.funcs.dpll = &vlv_dpll_funcs; in intel_dpll_init_clock_hook()
1807 dev_priv->display.funcs.dpll = &g4x_dpll_funcs; in intel_dpll_init_clock_hook()
1809 dev_priv->display.funcs.dpll = &pnv_dpll_funcs; in intel_dpll_init_clock_hook()
1811 dev_priv->display.funcs.dpll = &i9xx_dpll_funcs; in intel_dpll_init_clock_hook()
1813 dev_priv->display.funcs.dpll = &i8xx_dpll_funcs; in intel_dpll_init_clock_hook()
1827 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_enable_pll()
1828 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_enable_pll()
1829 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in i9xx_enable_pll()
1830 enum pipe pipe = crtc->pipe; in i9xx_enable_pll()
1833 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); in i9xx_enable_pll()
1835 /* PLL is protected by panel, make sure we can write it */ in i9xx_enable_pll()
1839 intel_de_write(dev_priv, FP0(pipe), hw_state->fp0); in i9xx_enable_pll()
1840 intel_de_write(dev_priv, FP1(pipe), hw_state->fp1); in i9xx_enable_pll()
1843 * Apparently we need to have VGA mode enabled prior to changing in i9xx_enable_pll()
1844 * the P1/P2 dividers. Otherwise the DPLL will keep using the old in i9xx_enable_pll()
1848 hw_state->dpll & ~DPLL_VGA_MODE_DIS); in i9xx_enable_pll()
1849 intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); in i9xx_enable_pll()
1857 hw_state->dpll_md); in i9xx_enable_pll()
1860 * DPLL is enabled and the clocks are stable. in i9xx_enable_pll()
1864 intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); in i9xx_enable_pll()
1869 intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); in i9xx_enable_pll()
1906 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_prepare_pll()
1907 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in vlv_prepare_pll()
1908 const struct dpll *clock = &crtc_state->dpll; in vlv_prepare_pll()
1909 enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe); in vlv_prepare_pll()
1910 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); in vlv_prepare_pll()
1911 enum pipe pipe = crtc->pipe; in vlv_prepare_pll()
1918 /* PLL B needs special handling */ in vlv_prepare_pll()
1925 /* Disable target IRef on PLL */ in vlv_prepare_pll()
1933 /* Set idtafcrecal before PLL is enabled */ in vlv_prepare_pll()
1934 tmp = DPIO_M1_DIV(clock->m1) | in vlv_prepare_pll()
1935 DPIO_M2_DIV(clock->m2) | in vlv_prepare_pll()
1936 DPIO_P1_DIV(clock->p1) | in vlv_prepare_pll()
1937 DPIO_P2_DIV(clock->p2) | in vlv_prepare_pll()
1938 DPIO_N_DIV(clock->n) | in vlv_prepare_pll()
1953 if (crtc_state->port_clock == 162000 || in vlv_prepare_pll()
1993 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in _vlv_enable_pll()
1994 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in _vlv_enable_pll()
1995 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in _vlv_enable_pll()
1996 enum pipe pipe = crtc->pipe; in _vlv_enable_pll()
1998 intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); in _vlv_enable_pll()
2003 drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe); in _vlv_enable_pll()
2009 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_enable_pll()
2010 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in vlv_enable_pll()
2011 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in vlv_enable_pll()
2012 enum pipe pipe = crtc->pipe; in vlv_enable_pll()
2014 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); in vlv_enable_pll()
2016 /* PLL is protected by panel, make sure we can write it */ in vlv_enable_pll()
2021 hw_state->dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); in vlv_enable_pll()
2023 if (hw_state->dpll & DPLL_VCO_ENABLE) { in vlv_enable_pll()
2028 intel_de_write(dev_priv, DPLL_MD(dev_priv, pipe), hw_state->dpll_md); in vlv_enable_pll()
2034 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in chv_prepare_pll()
2035 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in chv_prepare_pll()
2036 const struct dpll *clock = &crtc_state->dpll; in chv_prepare_pll()
2037 enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe); in chv_prepare_pll()
2038 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); in chv_prepare_pll()
2042 m2_frac = clock->m2 & 0x3fffff; in chv_prepare_pll()
2049 DPIO_CHV_P1_DIV(clock->p1) | in chv_prepare_pll()
2050 DPIO_CHV_P2_DIV(clock->p2) | in chv_prepare_pll()
2053 /* Feedback post-divider - m2 */ in chv_prepare_pll()
2055 DPIO_CHV_M2_DIV(clock->m2 >> 22)); in chv_prepare_pll()
2057 /* Feedback refclk divider - n and m1 */ in chv_prepare_pll()
2084 if (clock->vco == 5400000) { in chv_prepare_pll()
2089 } else if (clock->vco <= 6200000) { in chv_prepare_pll()
2094 } else if (clock->vco <= 6480000) { in chv_prepare_pll()
2123 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in _chv_enable_pll()
2124 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in _chv_enable_pll()
2125 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in _chv_enable_pll()
2126 enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe); in _chv_enable_pll()
2127 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); in _chv_enable_pll()
2128 enum pipe pipe = crtc->pipe; in _chv_enable_pll()
2141 * Need to wait > 100ns between dclkp clock enable bit and PLL enable. in _chv_enable_pll()
2145 /* Enable PLL */ in _chv_enable_pll()
2146 intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); in _chv_enable_pll()
2148 /* Check PLL is locked */ in _chv_enable_pll()
2150 drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe); in _chv_enable_pll()
2156 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in chv_enable_pll()
2157 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in chv_enable_pll()
2158 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in chv_enable_pll()
2159 enum pipe pipe = crtc->pipe; in chv_enable_pll()
2161 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); in chv_enable_pll()
2163 /* PLL is protected by panel, make sure we can write it */ in chv_enable_pll()
2168 hw_state->dpll & ~DPLL_VCO_ENABLE); in chv_enable_pll()
2170 if (hw_state->dpll & DPLL_VCO_ENABLE) { in chv_enable_pll()
2184 hw_state->dpll_md); in chv_enable_pll()
2186 dev_priv->display.state.chv_dpll_md[pipe] = hw_state->dpll_md; in chv_enable_pll()
2192 drm_WARN_ON(&dev_priv->drm, in chv_enable_pll()
2197 hw_state->dpll_md); in chv_enable_pll()
2203 * vlv_force_pll_on - forcibly enable just the PLL
2205 * @pipe: pipe PLL to enable
2206 * @dpll: PLL configuration
2208 * Enable the PLL for @pipe using the supplied @dpll config. To be used
2209 * in cases where we need the PLL enabled even when @pipe is not going to
2210 * be enabled.
2220 return -ENOMEM; in vlv_force_pll_on()
2222 crtc_state->cpu_transcoder = (enum transcoder)pipe; in vlv_force_pll_on()
2223 crtc_state->pixel_multiplier = 1; in vlv_force_pll_on()
2224 crtc_state->dpll = *dpll; in vlv_force_pll_on()
2225 crtc_state->output_types = BIT(INTEL_OUTPUT_EDP); in vlv_force_pll_on()
2235 intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi); in vlv_force_pll_on()
2285 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in i9xx_disable_pll()
2286 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_disable_pll()
2287 enum pipe pipe = crtc->pipe; in i9xx_disable_pll()
2294 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); in i9xx_disable_pll()
2302 * vlv_force_pll_off - forcibly disable just the PLL
2304 * @pipe: pipe PLL to disable
2306 * Disable the PLL for @pipe. To be used in cases where we need
2307 * the PLL enabled even when @pipe is not going to be enabled.
2317 /* Only for pre-ILK configs */
2325 "PLL state assertion failure (expected %s, current %s)\n", in assert_pll()