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/linux-6.12.1/drivers/i2c/busses/
Di2c-exynos5.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver
11 #include <linux/i2c.h>
33 * and for checking transfer status
205 /* Version of HS-I2C Hardware */
210 * struct exynos_hsi2c_variant - platform specific HSI2C driver data
212 * @hw: the hardware variant of Exynos I2C controller
245 .compatible = "samsung,exynos5-hsi2c",
248 .compatible = "samsung,exynos5250-hsi2c",
251 .compatible = "samsung,exynos5260-hsi2c",
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Di2c-rzv2m.c1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for the Renesas RZ/V2M I2C unit
5 * Copyright (C) 2016-2022 Renesas Electronics Corporation
15 #include <linux/i2c.h>
35 #define IICB0IICE BIT(7) /* I2C Enable */
92 complete(&priv->msg_tia_done); in rzv2m_i2c_tia_irq_handler()
111 pclk_hz = clk_get_rate(priv->clk); in rzv2m_i2c_clock_calculate()
120 priv->bus_mode = RZV2M_I2C_400K; in rzv2m_i2c_clock_calculate()
123 priv->bus_mode = RZV2M_I2C_100K; in rzv2m_i2c_clock_calculate()
126 dev_err(dev, "transfer speed is invalid\n"); in rzv2m_i2c_clock_calculate()
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Di2c-designware-master.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Synopsys DesignWare I2C adapter driver (master only).
5 * Based on the TI DAVINCI I2C adapter driver.
16 #include <linux/i2c.h>
27 #include "i2c-designware-core.h"
36 regmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2); in i2c_dw_configure_fifo_master()
37 regmap_write(dev->map, DW_IC_RX_TL, 0); in i2c_dw_configure_fifo_master()
39 /* Configure the I2C master */ in i2c_dw_configure_fifo_master()
40 regmap_write(dev->map, DW_IC_CON, dev->master_cfg); in i2c_dw_configure_fifo_master()
47 struct i2c_timings *t = &dev->timings; in i2c_dw_set_timings_master()
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Di2c-meson.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * I2C bus driver for Amlogic Meson SoCs
11 #include <linux/i2c.h>
21 /* Meson I2C register map */
68 * struct meson_i2c - Meson I2C device private data
70 * @adap: I2C adapter instance
74 * @msg: Pointer to the current I2C message
76 * @last: Flag set for the last message in the transfer
77 * @count: Number of bytes to be sent/received in current transfer
81 * @done: Completion used to wait for transfer termination
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Di2c-mxs.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale MXS I2C bus driver
5 * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
6 * Copyright (C) 2011-2012 Wolfram Sang, Pengutronix e.K.
8 * based on a (non-working) driver which was:
10 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
16 #include <linux/i2c.h>
25 #include <linux/dma-mapping.h>
27 #include <linux/dma/mxs-dma.h>
29 #define DRIVER_NAME "mxs-i2c"
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Di2c-mpc.c1 // SPDX-License-Identifier: GPL-2.0
3 * This is a combined i2c adapter and algorithm driver for the
5 * the same I2C unit (8240, 8245, 85xx).
7 * Copyright (C) 2003-2004 Humboldt Solutions Ltd, adrian@humboldt.co.uk
25 #include <linux/i2c.h>
109 void (*setup)(struct device_node *node, struct mpc_i2c *i2c, u32 clock);
112 static inline void writeccr(struct mpc_i2c *i2c, u32 x) in writeccr() argument
114 writeb(x, i2c->base + MPC_I2C_CR); in writeccr()
122 static void mpc_i2c_fixup(struct mpc_i2c *i2c) in mpc_i2c_fixup() argument
127 for (k = 9; k; k--) { in mpc_i2c_fixup()
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Di2c-st.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * I2C controller driver, used in STMicroelectronics devices.
13 #include <linux/i2c.h>
93 /* SSC I2C Control */
130 * struct st_i2c_timings - per-Mode tuning parameters
131 * @rate: I2C bus rate
132 * @rep_start_hold: I2C repeated start hold time requirement
133 * @rep_start_setup: I2C repeated start set up time requirement
134 * @start_hold: I2C start hold time requirement
135 * @data_setup_time: I2C data set up time requirement
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Di2c-cadence.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * I2C bus driver for the Cadence I2C controller.
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
10 #include <linux/i2c.h>
21 /* Register offsets for the I2C device. */
24 #define CDNS_I2C_ADDR_OFFSET 0x08 /* I2C Address Register, RW */
25 #define CDNS_I2C_DATA_OFFSET 0x0C /* I2C Data Register, RW */
27 #define CDNS_I2C_XFER_SIZE_OFFSET 0x14 /* Transfer Size Register, RW */
38 /* Read or Write Master transfer 0 = Transmitter, 1 = Receiver */
60 * I2C Address Register Bit mask definitions
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Di2c-s3c2410.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* linux/drivers/i2c/busses/i2c-s3c2410.c
7 * S3C2410 I2C Controller
13 #include <linux/i2c.h>
34 #include <linux/platform_data/i2c-s3c2410.h>
81 /* Max time to wait for bus to become idle after a xfer (in us) */
87 /* i2c controller state */
125 .name = "s3c2410-i2c",
128 .name = "s3c2440-i2c",
131 .name = "s3c2440-hdmiphy-i2c",
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Di2c-hisi.c1 // SPDX-License-Identifier: GPL-2.0
3 * HiSilicon I2C Controller Driver for Kunpeng SoC
12 #include <linux/i2c.h>
97 /* Intermediates for recording the transfer process */
108 /* I2C bus configuration */
116 writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_MASK); in hisi_i2c_enable_int()
121 writel_relaxed((~mask) & HISI_I2C_INT_ALL, ctlr->iobase + HISI_I2C_INT_MASK); in hisi_i2c_disable_int()
126 writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_CLR); in hisi_i2c_clear_int()
131 writel_relaxed(mask, ctlr->iobase + HISI_I2C_TX_INT_CLR); in hisi_i2c_clear_tx_int()
136 u32 int_err = ctlr->xfer_err, reg; in hisi_i2c_handle_errors()
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Di2c-designware-common.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Synopsys DesignWare I2C adapter driver.
5 * Based on the TI DAVINCI I2C adapter driver.
18 #include <linux/i2c.h>
34 #include "i2c-designware-core.h"
64 "incorrect slave-transmitter mode configuration",
71 *val = readl(dev->base + reg); in dw_reg_read()
80 writel(val, dev->base + reg); in dw_reg_write()
89 *val = swab32(readl(dev->base + reg)); in dw_reg_read_swab()
98 writel(swab32(val), dev->base + reg); in dw_reg_write_swab()
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Di2c-davinci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * TI DAVINCI I2C adapter driver.
10 * ----------------------------------------------------------------------------
12 * ----------------------------------------------------------------------------
17 #include <linux/i2c.h>
29 #include <linux/platform_data/i2c-davinci.h>
32 /* ----- global defines ----------------------------------------------- */
117 /* timeout for pm runtime autosuspend */
147 writew_relaxed(val, i2c_dev->base + reg); in davinci_i2c_write_reg()
152 return readw_relaxed(i2c_dev->base + reg); in davinci_i2c_read_reg()
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Di2c-nomadik.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2009 ST-Ericsson SA
6 * I2C master mode controller driver, used in Nomadik 8815
11 * - The memory bus only supports 32-bit accesses.
12 * - A register must be configured for the I2C speed mode;
22 #include <linux/i2c.h>
34 #define DRIVER_NAME "nmk-i2c"
36 /* I2C Controller register offsets */
73 #define I2C_MCR_A7 GENMASK(7, 1) /* 7-bit address */
74 #define I2C_MCR_EA10 GENMASK(10, 8) /* 10-bit Extended address */
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Di2c-gpio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Bitbanging I2C bus driver using the GPIO API
11 #include <linux/i2c-algo-bit.h>
12 #include <linux/i2c.h>
16 #include <linux/platform_data/i2c-gpio.h>
43 gpiod_set_value_cansleep(priv->sda, state); in i2c_gpio_setsda_val()
48 * for pins that are configured as open drain and for output-only
49 * pins. The latter case will break the i2c protocol, but it will
56 gpiod_set_value_cansleep(priv->scl, state); in i2c_gpio_setscl_val()
63 return gpiod_get_value_cansleep(priv->sda); in i2c_gpio_getsda()
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Di2c-imx.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2002 Motorola GSG-China
9 * Implementation of I2C Adapter/Algorithm Driver
10 * for I2C Bus integrated in Freescale i.MX/MXC processors
12 * Derived from Motorola GSG China I2C example driver
28 #include <linux/dma-mapping.h>
34 #include <linux/i2c.h>
46 #include <linux/platform_data/i2c-imx.h>
53 #define DRIVER_NAME "imx-i2c"
58 * Enable DMA if transfer byte size is bigger than this threshold.
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Di2c-emev2.c1 // SPDX-License-Identifier: GPL-2.0
3 * I2C driver for the Renesas EMEV2 SoC
5 * Copyright (C) 2015 Wolfram Sang <wsa@sang-engineering.com>
7 * Copyright 2010-2015 Renesas Electronics Corporation
13 #include <linux/i2c.h>
23 /* I2C Registers */
34 /* I2C IICACT0 Masks */
37 /* I2C IICC0 Masks */
46 /* I2C IICCL0 Masks */
50 /* I2C IICSE0 Masks */
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Di2c-pxa.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * I2C adapter for the PXA I2C bus access.
8 * Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
13 * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
14 * Jan 2003: added limited signal handling [Kai-Uwe Bloem]
24 #include <linux/i2c.h>
34 #include <linux/platform_data/i2c-pxa.h>
38 /* I2C register field definitions */
45 #define ICR_TB (1 << 3) /* transfer byte bit */
59 #define ICR_A3700_FM (1 << 16) /* fast mode for armada-3700 */
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Di2c-img-scb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * I2C adapter for the IMG Serial Control Bus (SCB) IP block.
7 * There are three ways that this I2C controller can be driven:
9 * - Raw control of the SDA and SCK signals.
15 * - Atomic commands. A low level I2C symbol (such as generate
20 * This mode of operation is used by MODE_ATOMIC, which uses an I2C
21 * state machine in the interrupt handler to compose/react to I2C
26 * in suboptimal use of the bus, with gaps between the I2C symbols while
29 * - Automatic mode. A bus address, and whether to read/write is
30 * specified, and the hardware takes care of the I2C state machine,
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Di2c-tegra.c1 // SPDX-License-Identifier: GPL-2.0
3 * drivers/i2c/busses/i2c-tegra.c
14 #include <linux/dma-mapping.h>
16 #include <linux/i2c.h>
51 #define I2C_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 5)
52 #define I2C_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 2)
130 #define I2C_MST_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 4)
131 #define I2C_MST_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 16)
137 /* configuration load timeout in microseconds */
144 * I2C Controller will use PIO mode for transfers up to 32 bytes in order to
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Di2c-qup.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2009-2013, 2016-2018, The Linux Foundation. All rights reserved.
14 #include <linux/dma-mapping.h>
16 #include <linux/i2c.h>
70 /* I2C mini core related values */
125 /* Maximum transfer length for single DMA descriptor */
128 /* Maximum transfer length for all DMA descriptors */
133 * Minimum transfer timeout for i2c transfers in seconds. It will be added on
134 * the top of maximum transfer time calculated from i2c bus speed to compensate
145 * data transfer
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Di2c-rcar.c1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for the Renesas R-Car I2C unit
5 * Copyright (C) 2014-19 Wolfram Sang <wsa@sang-engineering.com>
6 * Copyright (C) 2011-2019 Renesas Electronics Corporation
8 * Copyright (C) 2012-14 Renesas Solutions Corp.
11 * This file is based on the drivers/i2c/busses/i2c-sh7760.c
12 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
18 #include <linux/dma-mapping.h>
23 #include <linux/i2c.h>
24 #include <linux/i2c-smbus.h>
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/linux-6.12.1/Documentation/devicetree/bindings/i2c/
Di2c-mpc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-mpc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: I2C-Bus adapter for MPC824x/83xx/85xx/86xx/512x/52xx SoCs
10 - Chris Packham <chris.packham@alliedtelesis.co.nz>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
18 - items:
19 - enum:
20 - mpc5200-i2c
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/linux-6.12.1/drivers/gpu/drm/msm/hdmi/
Dhdmi_i2c.c1 // SPDX-License-Identifier: GPL-2.0-only
19 struct hdmi *hdmi = hdmi_i2c->hdmi; in init_ddc()
33 /* enable reference timer for 27us */ in init_ddc()
41 struct hdmi *hdmi = hdmi_i2c->hdmi; in ddc_clear_irq()
42 struct drm_device *dev = hdmi->dev; in ddc_clear_irq()
47 --retry; in ddc_clear_irq()
58 DRM_DEV_ERROR(dev->dev, "timeout waiting for DDC\n"); in ddc_clear_irq()
59 return -ETIMEDOUT; in ddc_clear_irq()
62 hdmi_i2c->sw_done = false; in ddc_clear_irq()
71 struct hdmi *hdmi = hdmi_i2c->hdmi; in sw_done()
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/linux-6.12.1/drivers/platform/chrome/
Dcros_ec_spi.c1 // SPDX-License-Identifier: GPL-2.0
24 * about 400-500us for the EC to respond there is not a lot of
28 * SPI transfer size is 256 bytes, so at 5MHz we need a response
29 * time of perhaps <320us (200 bytes / 1600 bits).
34 * Allow for a long time for the EC to respond. We support i2c
37 * on the other end and need to transfer ~256 bytes, then we need:
38 * 10 us/bit * ~10 bits/byte * ~256 bytes = ~25ms
43 * not directly passing i2c through, but it's too late for that for
50 * for this, clocking in at 2-3ms.
58 * need at least 70 us with the 16 MHz STM32 EC, so go with 200 us to be
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/linux-6.12.1/drivers/comedi/drivers/
Ds626.c1 // SPDX-License-Identifier: GPL-2.0+
6 * COMEDI - Linux Control and Measurement Device Interface
10 * Copyright (C) 2002-2004 Sensoray Co., Inc.
68 * struct s626_private - Working data for s626 driver.
69 * @ai_cmd_running: non-zero if ai_cmd is running.
80 * @i2c_adrs: I2C device address for onboard EEPROM (board rev dependent)
98 #define S626_INDXMASK(C) (1 << (((C) > 2) ? ((C) * 2 - 1) : ((C) * 2 + 4)))
110 writel(val, dev->mmio + reg); in s626_mc_enable()
116 writel(cmd << 16, dev->mmio + reg); in s626_mc_disable()
124 val = readl(dev->mmio + reg); in s626_mc_test()
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