1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * Synopsys DesignWare I2C adapter driver.
5  * Based on the TI DAVINCI I2C adapter driver.
18 #include <linux/i2c.h>
34 #include "i2c-designware-core.h"
64 		"incorrect slave-transmitter mode configuration",
71 	*val = readl(dev->base + reg);  in dw_reg_read()
80 	writel(val, dev->base + reg);  in dw_reg_write()
89 	*val = swab32(readl(dev->base + reg));  in dw_reg_read_swab()
98 	writel(swab32(val), dev->base + reg);  in dw_reg_write_swab()
107 	*val = readw(dev->base + reg) |  in dw_reg_read_word()
108 		(readw(dev->base + reg + 2) << 16);  in dw_reg_read_word()
117 	writew(val, dev->base + reg);  in dw_reg_write_word()
118 	writew(val >> 16, dev->base + reg + 2);  in dw_reg_write_word()
124  * i2c_dw_init_regmap() - Initialize registers map
149 	if (dev->map)  in i2c_dw_init_regmap()
156 	reg = readl(dev->base + DW_IC_COMP_TYPE);  in i2c_dw_init_regmap()
159 	if ((dev->flags & MODEL_MASK) == MODEL_AMD_NAVI_GPU)  in i2c_dw_init_regmap()
169 		dev_err(dev->dev,  in i2c_dw_init_regmap()
171 		return -ENODEV;  in i2c_dw_init_regmap()
177 	 * basically we have MMIO-based regmap so non of the read/write methods  in i2c_dw_init_regmap()
180 	dev->map = devm_regmap_init(dev->dev, NULL, dev, &map_cfg);  in i2c_dw_init_regmap()
181 	if (IS_ERR(dev->map)) {  in i2c_dw_init_regmap()
182 		dev_err(dev->dev, "Failed to init the registers map\n");  in i2c_dw_init_regmap()
183 		return PTR_ERR(dev->map);  in i2c_dw_init_regmap()
198 	struct i2c_timings *t = &dev->timings;  in i2c_dw_validate_speed()
206 		if (t->bus_freq_hz == supported_speeds[i])  in i2c_dw_validate_speed()
210 	dev_err(dev->dev,  in i2c_dw_validate_speed()
212 		t->bus_freq_hz);  in i2c_dw_validate_speed()
214 	return -EINVAL;  in i2c_dw_validate_speed()
227 	writel((dev->sda_hold_time << 1) | MSCC_ICPU_CFG_TWI_DELAY_ENABLE,  in mscc_twi_set_sda_hold_time()
228 	       dev->ext + MSCC_ICPU_CFG_TWI_DELAY);  in mscc_twi_set_sda_hold_time()
238 	switch (dev->flags & MODEL_MASK) {  in i2c_dw_of_configure()
240 		dev->ext = devm_platform_ioremap_resource(pdev, 1);  in i2c_dw_of_configure()
241 		if (!IS_ERR(dev->ext))  in i2c_dw_of_configure()
242 			dev->set_sda_hold_time = mscc_twi_set_sda_hold_time;  in i2c_dw_of_configure()
289 	if (obj->type == ACPI_TYPE_PACKAGE && obj->package.count == 3) {  in i2c_dw_acpi_params()
290 		const union acpi_object *objs = obj->package.elements;  in i2c_dw_acpi_params()
303 	struct i2c_timings *t = &dev->timings;  in i2c_dw_acpi_configure()
310 	i2c_dw_acpi_params(device, "SSCN", &dev->ss_hcnt, &dev->ss_lcnt, &ss_ht);  in i2c_dw_acpi_configure()
311 	i2c_dw_acpi_params(device, "FMCN", &dev->fs_hcnt, &dev->fs_lcnt, &fs_ht);  in i2c_dw_acpi_configure()
312 	i2c_dw_acpi_params(device, "FPCN", &dev->fp_hcnt, &dev->fp_lcnt, &fp_ht);  in i2c_dw_acpi_configure()
313 	i2c_dw_acpi_params(device, "HSCN", &dev->hs_hcnt, &dev->hs_lcnt, &hs_ht);  in i2c_dw_acpi_configure()
315 	switch (t->bus_freq_hz) {  in i2c_dw_acpi_configure()
317 		dev->sda_hold_time = ss_ht;  in i2c_dw_acpi_configure()
320 		dev->sda_hold_time = fp_ht;  in i2c_dw_acpi_configure()
323 		dev->sda_hold_time = hs_ht;  in i2c_dw_acpi_configure()
327 		dev->sda_hold_time = fs_ht;  in i2c_dw_acpi_configure()
360 	u32 acpi_speed = i2c_dw_acpi_round_bus_speed(dev->dev);  in i2c_dw_adjust_bus_speed()
361 	struct i2c_timings *t = &dev->timings;  in i2c_dw_adjust_bus_speed()
364 	 * Find bus speed from the "clock-frequency" device property, ACPI  in i2c_dw_adjust_bus_speed()
367 	if (acpi_speed && t->bus_freq_hz)  in i2c_dw_adjust_bus_speed()
368 		t->bus_freq_hz = min(t->bus_freq_hz, acpi_speed);  in i2c_dw_adjust_bus_speed()
369 	else if (acpi_speed || t->bus_freq_hz)  in i2c_dw_adjust_bus_speed()
370 		t->bus_freq_hz = max(t->bus_freq_hz, acpi_speed);  in i2c_dw_adjust_bus_speed()
372 		t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ;  in i2c_dw_adjust_bus_speed()
377 	struct i2c_timings *t = &dev->timings;  in i2c_dw_fw_parse_and_configure()
378 	struct device *device = dev->dev;  in i2c_dw_fw_parse_and_configure()
403 	ret = regmap_read(dev->map, reg, &val);  in i2c_dw_read_scl_reg()
416 	 * DesignWare I2C core doesn't seem to have solid strategy to meet  in i2c_dw_scl_hcnt()
427 		 * configuration.  The resulting I2C bus speed will be  in i2c_dw_scl_hcnt()
432 		return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * tSYMBOL, MICRO) -  in i2c_dw_scl_hcnt()
449 		return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * (tSYMBOL + tf), MICRO) -  in i2c_dw_scl_hcnt()
464 	 * DW I2C core starts counting the SCL CNTs for the LOW period  in i2c_dw_scl_lcnt()
468 	 * should be 0.3 us, for safety.  in i2c_dw_scl_lcnt()
470 	return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * (tLOW + tf), MICRO) -  in i2c_dw_scl_lcnt()
484 	ret = regmap_read(dev->map, DW_IC_COMP_VERSION, &reg);  in i2c_dw_set_sda_hold()
489 		if (!dev->sda_hold_time) {  in i2c_dw_set_sda_hold()
491 			ret = regmap_read(dev->map, DW_IC_SDA_HOLD,  in i2c_dw_set_sda_hold()
492 					  &dev->sda_hold_time);  in i2c_dw_set_sda_hold()
498 		 * Workaround for avoiding TX arbitration lost in case I2C  in i2c_dw_set_sda_hold()
500 		 * SCL by enabling non-zero SDA RX hold. Specification says it  in i2c_dw_set_sda_hold()
504 		if (!(dev->sda_hold_time & DW_IC_SDA_HOLD_RX_MASK))  in i2c_dw_set_sda_hold()
505 			dev->sda_hold_time |= 1 << DW_IC_SDA_HOLD_RX_SHIFT;  in i2c_dw_set_sda_hold()
507 		dev_dbg(dev->dev, "SDA Hold Time TX:RX = %d:%d\n",  in i2c_dw_set_sda_hold()
508 			dev->sda_hold_time & ~(u32)DW_IC_SDA_HOLD_RX_MASK,  in i2c_dw_set_sda_hold()
509 			dev->sda_hold_time >> DW_IC_SDA_HOLD_RX_SHIFT);  in i2c_dw_set_sda_hold()
510 	} else if (dev->set_sda_hold_time) {  in i2c_dw_set_sda_hold()
511 		dev->set_sda_hold_time(dev);  in i2c_dw_set_sda_hold()
512 	} else if (dev->sda_hold_time) {  in i2c_dw_set_sda_hold()
513 		dev_warn(dev->dev,  in i2c_dw_set_sda_hold()
515 		dev->sda_hold_time = 0;  in i2c_dw_set_sda_hold()
526 	struct i2c_timings *t = &dev->timings;  in __i2c_dw_disable()
529 	int timeout = 100;  in __i2c_dw_disable()  local
534 	regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &raw_intr_stats);  in __i2c_dw_disable()
535 	regmap_read(dev->map, DW_IC_STATUS, &ic_stats);  in __i2c_dw_disable()
536 	regmap_read(dev->map, DW_IC_ENABLE, &enable);  in __i2c_dw_disable()
542 			regmap_write(dev->map, DW_IC_ENABLE, DW_IC_ENABLE_ENABLE);  in __i2c_dw_disable()
544 			 * Wait 10 times the signaling period of the highest I2C  in __i2c_dw_disable()
545 			 * transfer supported by the driver (for 400KHz this is  in __i2c_dw_disable()
546 			 * 25us) to ensure the I2C ENABLE bit is already set  in __i2c_dw_disable()
547 			 * as described in the DesignWare I2C databook.  in __i2c_dw_disable()
549 			fsleep(DIV_ROUND_CLOSEST_ULL(10 * MICRO, t->bus_freq_hz));  in __i2c_dw_disable()
554 		regmap_write(dev->map, DW_IC_ENABLE, enable | DW_IC_ENABLE_ABORT);  in __i2c_dw_disable()
555 		ret = regmap_read_poll_timeout(dev->map, DW_IC_ENABLE, enable,  in __i2c_dw_disable()
559 			dev_err(dev->dev, "timeout while trying to abort current transfer\n");  in __i2c_dw_disable()
568 		regmap_read(dev->map, DW_IC_ENABLE_STATUS, &status);  in __i2c_dw_disable()
573 		 * Wait 10 times the signaling period of the highest I2C  in __i2c_dw_disable()
574 		 * transfer supported by the driver (for 400KHz this is  in __i2c_dw_disable()
575 		 * 25us) as described in the DesignWare I2C databook.  in __i2c_dw_disable()
578 	} while (timeout--);  in __i2c_dw_disable()
580 	dev_warn(dev->dev, "timeout in disabling adapter\n");  in __i2c_dw_disable()
589 	if (WARN_ON_ONCE(!dev->get_clk_rate_khz))  in i2c_dw_clk_rate()
591 	return dev->get_clk_rate_khz(dev);  in i2c_dw_clk_rate()
600 		ret = clk_prepare_enable(dev->pclk);  in i2c_dw_prepare_clk()
604 		ret = clk_prepare_enable(dev->clk);  in i2c_dw_prepare_clk()
606 			clk_disable_unprepare(dev->pclk);  in i2c_dw_prepare_clk()
611 	clk_disable_unprepare(dev->clk);  in i2c_dw_prepare_clk()
612 	clk_disable_unprepare(dev->pclk);  in i2c_dw_prepare_clk()
622 	if (!dev->acquire_lock)  in i2c_dw_acquire_lock()
625 	ret = dev->acquire_lock();  in i2c_dw_acquire_lock()
629 	dev_err(dev->dev, "couldn't acquire bus ownership\n");  in i2c_dw_acquire_lock()
636 	if (dev->release_lock)  in i2c_dw_release_lock()
637 		dev->release_lock();  in i2c_dw_release_lock()
648 	ret = regmap_read_poll_timeout(dev->map, DW_IC_STATUS, status,  in i2c_dw_wait_bus_not_busy()
652 		dev_warn(dev->dev, "timeout waiting for bus ready\n");  in i2c_dw_wait_bus_not_busy()
654 		i2c_recover_bus(&dev->adapter);  in i2c_dw_wait_bus_not_busy()
656 		regmap_read(dev->map, DW_IC_STATUS, &status);  in i2c_dw_wait_bus_not_busy()
666 	unsigned long abort_source = dev->abort_source;  in i2c_dw_handle_tx_abort()
671 			dev_dbg(dev->dev,  in i2c_dw_handle_tx_abort()
673 		return -EREMOTEIO;  in i2c_dw_handle_tx_abort()
677 		dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]);  in i2c_dw_handle_tx_abort()
680 		return -EAGAIN;  in i2c_dw_handle_tx_abort()
682 		return -EINVAL; /* wrong msgs[] data */  in i2c_dw_handle_tx_abort()
684 		return -EIO;  in i2c_dw_handle_tx_abort()
694 	if ((dev->flags & MODEL_MASK) == MODEL_WANGXUN_SP) {  in i2c_dw_set_fifo_size()
695 		dev->tx_fifo_depth = TXGBE_TX_FIFO_DEPTH;  in i2c_dw_set_fifo_size()
696 		dev->rx_fifo_depth = TXGBE_RX_FIFO_DEPTH;  in i2c_dw_set_fifo_size()
709 	ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, &param);  in i2c_dw_set_fifo_size()
716 	if (!dev->tx_fifo_depth) {  in i2c_dw_set_fifo_size()
717 		dev->tx_fifo_depth = tx_fifo_depth;  in i2c_dw_set_fifo_size()
718 		dev->rx_fifo_depth = rx_fifo_depth;  in i2c_dw_set_fifo_size()
720 		dev->tx_fifo_depth = min_t(u32, dev->tx_fifo_depth,  in i2c_dw_set_fifo_size()
722 		dev->rx_fifo_depth = min_t(u32, dev->rx_fifo_depth,  in i2c_dw_set_fifo_size()
733 	return dev->functionality;  in i2c_dw_func()
750 	regmap_read(dev->map, DW_IC_CLR_INTR, &dummy);  in i2c_dw_disable()
758 	device_set_node(&dev->adapter.dev, dev_fwnode(dev->dev));  in i2c_dw_probe()
760 	switch (dev->mode) {  in i2c_dw_probe()
766 		dev_err(dev->dev, "Wrong operation mode: %d\n", dev->mode);  in i2c_dw_probe()
767 		return -EINVAL;  in i2c_dw_probe()
777 	 * I2C operation regions, so tell the PM core and middle layers to  in i2c_dw_prepare()
787 	if (dev->shared_with_punit)  in i2c_dw_runtime_suspend()
800 	i2c_mark_adapter_suspended(&dev->adapter);  in i2c_dw_suspend()
809 	if (!dev->shared_with_punit)  in i2c_dw_runtime_resume()
812 	dev->init(dev);  in i2c_dw_runtime_resume()
822 	i2c_mark_adapter_resumed(&dev->adapter);  in i2c_dw_resume()
833 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core");