Lines Matching +full:i2c +full:- +full:transfer +full:- +full:timeout +full:- +full:us
1 // SPDX-License-Identifier: GPL-2.0
3 * HiSilicon I2C Controller Driver for Kunpeng SoC
12 #include <linux/i2c.h>
97 /* Intermediates for recording the transfer process */
108 /* I2C bus configuration */
116 writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_MASK); in hisi_i2c_enable_int()
121 writel_relaxed((~mask) & HISI_I2C_INT_ALL, ctlr->iobase + HISI_I2C_INT_MASK); in hisi_i2c_disable_int()
126 writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_CLR); in hisi_i2c_clear_int()
131 writel_relaxed(mask, ctlr->iobase + HISI_I2C_TX_INT_CLR); in hisi_i2c_clear_tx_int()
136 u32 int_err = ctlr->xfer_err, reg; in hisi_i2c_handle_errors()
139 reg = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); in hisi_i2c_handle_errors()
142 dev_err(ctlr->dev, "rx fifo error read\n"); in hisi_i2c_handle_errors()
145 dev_err(ctlr->dev, "rx fifo error write\n"); in hisi_i2c_handle_errors()
148 dev_err(ctlr->dev, "tx fifo error read\n"); in hisi_i2c_handle_errors()
151 dev_err(ctlr->dev, "tx fifo error write\n"); in hisi_i2c_handle_errors()
157 struct i2c_msg *msg = ctlr->msgs; in hisi_i2c_start_xfer()
160 reg = readl(ctlr->iobase + HISI_I2C_FRAME_CTRL); in hisi_i2c_start_xfer()
162 if (msg->flags & I2C_M_TEN) in hisi_i2c_start_xfer()
164 writel(reg, ctlr->iobase + HISI_I2C_FRAME_CTRL); in hisi_i2c_start_xfer()
166 reg = readl(ctlr->iobase + HISI_I2C_SLV_ADDR); in hisi_i2c_start_xfer()
168 reg |= FIELD_PREP(HISI_I2C_SLV_ADDR_VAL, msg->addr); in hisi_i2c_start_xfer()
169 writel(reg, ctlr->iobase + HISI_I2C_SLV_ADDR); in hisi_i2c_start_xfer()
171 reg = readl(ctlr->iobase + HISI_I2C_FIFO_CTRL); in hisi_i2c_start_xfer()
173 writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL); in hisi_i2c_start_xfer()
175 writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL); in hisi_i2c_start_xfer()
186 ctlr->msg_num = 0; in hisi_i2c_reset_xfer()
187 ctlr->xfer_err = 0; in hisi_i2c_reset_xfer()
188 ctlr->msg_tx_idx = 0; in hisi_i2c_reset_xfer()
189 ctlr->msg_rx_idx = 0; in hisi_i2c_reset_xfer()
190 ctlr->buf_tx_idx = 0; in hisi_i2c_reset_xfer()
191 ctlr->buf_rx_idx = 0; in hisi_i2c_reset_xfer()
195 * Initialize the transfer information and start the I2C bus transfer.
196 * We only configure the transfer and do some pre/post works here, and
197 * wait for the transfer done. The major transfer process is performed
208 ctlr->completion = &done; in hisi_i2c_xfer()
209 ctlr->msg_num = num; in hisi_i2c_xfer()
210 ctlr->msgs = msgs; in hisi_i2c_xfer()
214 if (!wait_for_completion_timeout(ctlr->completion, adap->timeout)) { in hisi_i2c_xfer()
216 synchronize_irq(ctlr->irq); in hisi_i2c_xfer()
217 i2c_recover_bus(&ctlr->adapter); in hisi_i2c_xfer()
218 dev_err(ctlr->dev, "bus transfer timeout\n"); in hisi_i2c_xfer()
219 ret = -EIO; in hisi_i2c_xfer()
222 if (ctlr->xfer_err) { in hisi_i2c_xfer()
224 ret = -EIO; in hisi_i2c_xfer()
228 ctlr->completion = NULL; in hisi_i2c_xfer()
248 while (ctlr->msg_rx_idx < ctlr->msg_num) { in hisi_i2c_read_rx_fifo()
249 cur_msg = ctlr->msgs + ctlr->msg_rx_idx; in hisi_i2c_read_rx_fifo()
251 if (!(cur_msg->flags & I2C_M_RD)) { in hisi_i2c_read_rx_fifo()
252 ctlr->msg_rx_idx++; in hisi_i2c_read_rx_fifo()
256 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); in hisi_i2c_read_rx_fifo()
258 ctlr->buf_rx_idx < cur_msg->len) { in hisi_i2c_read_rx_fifo()
259 cur_msg->buf[ctlr->buf_rx_idx++] = readl(ctlr->iobase + HISI_I2C_RXDATA); in hisi_i2c_read_rx_fifo()
260 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); in hisi_i2c_read_rx_fifo()
263 if (ctlr->buf_rx_idx == cur_msg->len) { in hisi_i2c_read_rx_fifo()
264 ctlr->buf_rx_idx = 0; in hisi_i2c_read_rx_fifo()
265 ctlr->msg_rx_idx++; in hisi_i2c_read_rx_fifo()
277 int max_write = HISI_I2C_TX_FIFO_DEPTH - HISI_I2C_TX_F_AE_THRESH; in hisi_i2c_xfer_msg()
282 while (ctlr->msg_tx_idx < ctlr->msg_num) { in hisi_i2c_xfer_msg()
283 cur_msg = ctlr->msgs + ctlr->msg_tx_idx; in hisi_i2c_xfer_msg()
284 last_msg = (ctlr->msg_tx_idx == ctlr->msg_num - 1); in hisi_i2c_xfer_msg()
287 if (ctlr->msg_tx_idx && !ctlr->buf_tx_idx) in hisi_i2c_xfer_msg()
290 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); in hisi_i2c_xfer_msg()
292 ctlr->buf_tx_idx < cur_msg->len && max_write) { in hisi_i2c_xfer_msg()
301 if (ctlr->buf_tx_idx == cur_msg->len - 1 && last_msg) in hisi_i2c_xfer_msg()
304 if (cur_msg->flags & I2C_M_RD) in hisi_i2c_xfer_msg()
308 cur_msg->buf[ctlr->buf_tx_idx]); in hisi_i2c_xfer_msg()
310 writel(cmd, ctlr->iobase + HISI_I2C_CMD_TXDATA); in hisi_i2c_xfer_msg()
311 ctlr->buf_tx_idx++; in hisi_i2c_xfer_msg()
312 max_write--; in hisi_i2c_xfer_msg()
314 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); in hisi_i2c_xfer_msg()
317 /* Update the transfer index after per message transfer is done. */ in hisi_i2c_xfer_msg()
318 if (ctlr->buf_tx_idx == cur_msg->len) { in hisi_i2c_xfer_msg()
319 ctlr->buf_tx_idx = 0; in hisi_i2c_xfer_msg()
320 ctlr->msg_tx_idx++; in hisi_i2c_xfer_msg()
332 if (ctlr->msg_tx_idx == ctlr->msg_num) in hisi_i2c_xfer_msg()
344 * Don't handle the interrupt if cltr->completion is NULL. We may in hisi_i2c_irq()
345 * reach here because the interrupt is spurious or the transfer is in hisi_i2c_irq()
346 * started by another port (e.g. firmware) rather than us. in hisi_i2c_irq()
348 if (!ctlr->completion) in hisi_i2c_irq()
351 int_stat = readl(ctlr->iobase + HISI_I2C_INT_MSTAT); in hisi_i2c_irq()
360 ctlr->xfer_err = int_stat; in hisi_i2c_irq()
364 /* Drain the rx fifo before finish the transfer */ in hisi_i2c_irq()
377 complete(ctlr->completion); in hisi_i2c_irq()
397 total_cnt = DIV_ROUND_UP_ULL(ctlr->clk_rate_khz * HZ_PER_KHZ, ctlr->t.bus_freq_hz); in hisi_i2c_set_scl()
401 t_scl_lcnt = total_cnt - t_scl_hcnt; in hisi_i2c_set_scl()
403 scl_fall_cnt = NSEC_TO_CYCLES(ctlr->t.scl_fall_ns, ctlr->clk_rate_khz); in hisi_i2c_set_scl()
405 scl_rise_cnt = NSEC_TO_CYCLES(ctlr->t.scl_rise_ns, ctlr->clk_rate_khz); in hisi_i2c_set_scl()
408 scl_hcnt = t_scl_hcnt - ctlr->spk_len - 7 - scl_fall_cnt; in hisi_i2c_set_scl()
409 scl_lcnt = t_scl_lcnt - 1 - scl_rise_cnt; in hisi_i2c_set_scl()
411 writel(scl_hcnt, ctlr->iobase + reg_hcnt); in hisi_i2c_set_scl()
412 writel(scl_lcnt, ctlr->iobase + reg_lcnt); in hisi_i2c_set_scl()
419 i2c_parse_fw_timings(ctlr->dev, &ctlr->t, true); in hisi_i2c_configure_bus()
420 ctlr->spk_len = NSEC_TO_CYCLES(ctlr->t.digital_filter_width_ns, ctlr->clk_rate_khz); in hisi_i2c_configure_bus()
422 switch (ctlr->t.bus_freq_hz) { in hisi_i2c_configure_bus()
436 ctlr->t.bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ; in hisi_i2c_configure_bus()
441 reg = readl(ctlr->iobase + HISI_I2C_FRAME_CTRL); in hisi_i2c_configure_bus()
444 writel(reg, ctlr->iobase + HISI_I2C_FRAME_CTRL); in hisi_i2c_configure_bus()
446 sda_hold_cnt = NSEC_TO_CYCLES(ctlr->t.sda_hold_ns, ctlr->clk_rate_khz); in hisi_i2c_configure_bus()
449 writel(reg, ctlr->iobase + HISI_I2C_SDA_HOLD); in hisi_i2c_configure_bus()
451 writel(ctlr->spk_len, ctlr->iobase + HISI_I2C_FS_SPK_LEN); in hisi_i2c_configure_bus()
455 writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL); in hisi_i2c_configure_bus()
461 struct device *dev = &pdev->dev; in hisi_i2c_probe()
469 return -ENOMEM; in hisi_i2c_probe()
471 ctlr->iobase = devm_platform_ioremap_resource(pdev, 0); in hisi_i2c_probe()
472 if (IS_ERR(ctlr->iobase)) in hisi_i2c_probe()
473 return PTR_ERR(ctlr->iobase); in hisi_i2c_probe()
475 ctlr->irq = platform_get_irq(pdev, 0); in hisi_i2c_probe()
476 if (ctlr->irq < 0) in hisi_i2c_probe()
477 return ctlr->irq; in hisi_i2c_probe()
479 ctlr->dev = dev; in hisi_i2c_probe()
483 ret = devm_request_irq(dev, ctlr->irq, hisi_i2c_irq, 0, "hisi-i2c", ctlr); in hisi_i2c_probe()
487 ctlr->clk = devm_clk_get_optional_enabled(&pdev->dev, NULL); in hisi_i2c_probe()
488 if (IS_ERR_OR_NULL(ctlr->clk)) { in hisi_i2c_probe()
493 clk_rate_hz = clk_get_rate(ctlr->clk); in hisi_i2c_probe()
496 ctlr->clk_rate_khz = DIV_ROUND_UP_ULL(clk_rate_hz, HZ_PER_KHZ); in hisi_i2c_probe()
500 adapter = &ctlr->adapter; in hisi_i2c_probe()
501 snprintf(adapter->name, sizeof(adapter->name), in hisi_i2c_probe()
502 "HiSilicon I2C Controller %s", dev_name(dev)); in hisi_i2c_probe()
503 adapter->owner = THIS_MODULE; in hisi_i2c_probe()
504 adapter->algo = &hisi_i2c_algo; in hisi_i2c_probe()
505 adapter->dev.parent = dev; in hisi_i2c_probe()
512 hw_version = readl(ctlr->iobase + HISI_I2C_VERSION); in hisi_i2c_probe()
513 dev_info(ctlr->dev, "speed mode is %s. hw version 0x%x\n", in hisi_i2c_probe()
514 i2c_freq_mode_string(ctlr->t.bus_freq_hz), hw_version); in hisi_i2c_probe()
526 { .compatible = "hisilicon,ascend910-i2c", },
534 .name = "hisi-i2c",
542 MODULE_DESCRIPTION("HiSilicon I2C Controller Driver");