1 // SPDX-License-Identifier: GPL-2.0-only
3  * Copyright (C) 2009 ST-Ericsson SA
6  * I2C master mode controller driver, used in Nomadik 8815
11  *  - The memory bus only supports 32-bit accesses.
12  *  - A register must be configured for the I2C speed mode;
22 #include <linux/i2c.h>
34 #define DRIVER_NAME "nmk-i2c"
36 /* I2C Controller register offsets */
73 #define I2C_MCR_A7		GENMASK(7, 1)	/* 7-bit address */
74 #define I2C_MCR_EA10		GENMASK(10, 8)	/* 10-bit Extended address */
85 #define I2C_SR_LENGTH		GENMASK(19, 9)	/* Transfer length */
87 /* Baud-rate counter register (BRCR) */
88 #define I2C_BRCR_BRCNT1		GENMASK(31, 16)	/* Baud-rate counter 1 */
89 #define I2C_BRCR_BRCNT2		GENMASK(15, 0)	/* Baud-rate counter 2 */
131  * struct i2c_vendor_data - per-vendor variations
161  * struct i2c_nmk_client - client specific data
162  * @slave_adr: 7-bit slave address
166  * @operation: current I2C operation
177  * struct nmk_i2c_dev - private data structure of the controller.
180  * @adap: corresponding I2C adapter.
183  * @clk: hardware i2c block clock.
188  * @timeout_usecs: Slave response timeout
194  * @has_32b_bus: controller is on a bus that only supports 32-bit accesses.
240 	if (priv->has_32b_bus)  in nmk_i2c_readb()
241 		return readl(priv->virtbase + reg);  in nmk_i2c_readb()
243 		return readb(priv->virtbase + reg);  in nmk_i2c_readb()
249 	if (priv->has_32b_bus)  in nmk_i2c_writeb()
250 		writel(val, priv->virtbase + reg);  in nmk_i2c_writeb()
252 		writeb(val, priv->virtbase + reg);  in nmk_i2c_writeb()
256  * flush_i2c_fifo() - This function flushes the I2C FIFO
257  * @priv: private data of I2C Driver
259  * This function flushes the I2C Tx and Rx FIFOs. It returns
265 	ktime_t timeout;  in flush_i2c_fifo()  local
271 	 * On the completion, the I2C internal logic clears these  in flush_i2c_fifo()
275 	writel((I2C_CR_FTX | I2C_CR_FRX), priv->virtbase + I2C_CR);  in flush_i2c_fifo()
278 		timeout = ktime_add_us(ktime_get(), priv->timeout_usecs);  in flush_i2c_fifo()
280 		while (ktime_after(timeout, ktime_get())) {  in flush_i2c_fifo()
281 			if ((readl(priv->virtbase + I2C_CR) &  in flush_i2c_fifo()
287 	dev_err(&priv->adev->dev,  in flush_i2c_fifo()
291 	return -ETIMEDOUT;  in flush_i2c_fifo()
295  * disable_all_interrupts() - Disable all interrupts of this I2c Bus
296  * @priv: private data of I2C Driver
300 	writel(0, priv->virtbase + I2C_IMSCR);  in disable_all_interrupts()
304  * clear_all_interrupts() - Clear all interrupts of I2C Controller
305  * @priv: private data of I2C Driver
309 	writel(I2C_CLEAR_ALL_INTS, priv->virtbase + I2C_ICR);  in clear_all_interrupts()
313  * init_hw() - initialize the I2C hardware
314  * @priv: private data of I2C Driver
325 	i2c_clr_bit(priv->virtbase + I2C_CR, I2C_CR_PE);  in init_hw()
331 	priv->cli.operation = I2C_NO_OPERATION;  in init_hw()
340 /* grab top three bits from extended I2C addresses */
344  * load_i2c_mcr_reg() - load the MCR register
353 	mcr |= FIELD_PREP(I2C_MCR_A7, priv->cli.slave_adr);  in load_i2c_mcr_reg()
356 		/* 10-bit address transaction */  in load_i2c_mcr_reg()
365 						priv->cli.slave_adr);  in load_i2c_mcr_reg()
369 		/* 7-bit address transaction */  in load_i2c_mcr_reg()
377 	if (priv->cli.operation == I2C_WRITE)  in load_i2c_mcr_reg()
383 	if (priv->stop)  in load_i2c_mcr_reg()
388 	mcr |= FIELD_PREP(I2C_MCR_LENGTH, priv->cli.count);  in load_i2c_mcr_reg()
394  * setup_i2c_controller() - setup the controller
404 	writel(0x0, priv->virtbase + I2C_CR);  in setup_i2c_controller()
405 	writel(0x0, priv->virtbase + I2C_HSMCR);  in setup_i2c_controller()
406 	writel(0x0, priv->virtbase + I2C_TFTR);  in setup_i2c_controller()
407 	writel(0x0, priv->virtbase + I2C_RFTR);  in setup_i2c_controller()
408 	writel(0x0, priv->virtbase + I2C_DMAR);  in setup_i2c_controller()
410 	i2c_clk = clk_get_rate(priv->clk);  in setup_i2c_controller()
416 	 * stretching in terms of i2c clk cycles + 1 (zero means  in setup_i2c_controller()
425 	switch (priv->sm) {  in setup_i2c_controller()
440 	dev_dbg(&priv->adev->dev, "calculated SLSU = %04x\n", slsu);  in setup_i2c_controller()
441 	writel(FIELD_PREP(I2C_SCR_SLSU, slsu), priv->virtbase + I2C_SCR);  in setup_i2c_controller()
446 	 * operation. TODO - high speed support.  in setup_i2c_controller()
448 	div = (priv->clk_freq > I2C_MAX_STANDARD_MODE_FREQ) ? 3 : 2;  in setup_i2c_controller()
458 	brcr2 = FIELD_PREP(I2C_BRCR_BRCNT2, i2c_clk / (priv->clk_freq * div));  in setup_i2c_controller()
461 	writel((brcr1 | brcr2), priv->virtbase + I2C_BRCR);  in setup_i2c_controller()
466 	 * TODO - support for fast mode plus (up to 1Mb/s)  in setup_i2c_controller()
469 	if (priv->sm > I2C_FREQ_MODE_FAST) {  in setup_i2c_controller()
470 		dev_err(&priv->adev->dev,  in setup_i2c_controller()
474 		writel((brcr1 | brcr2), priv->virtbase + I2C_BRCR);  in setup_i2c_controller()
476 		       priv->virtbase + I2C_CR);  in setup_i2c_controller()
478 	writel(FIELD_PREP(I2C_CR_SM, priv->sm), priv->virtbase + I2C_CR);  in setup_i2c_controller()
481 	writel(priv->tft, priv->virtbase + I2C_TFTR);  in setup_i2c_controller()
482 	writel(priv->rft, priv->virtbase + I2C_RFTR);  in setup_i2c_controller()
487 	if (priv->timeout_usecs < jiffies_to_usecs(1)) {  in nmk_i2c_wait_xfer_done()
488 		unsigned long timeout_usecs = priv->timeout_usecs;  in nmk_i2c_wait_xfer_done()
489 		ktime_t timeout = ktime_set(0, timeout_usecs * NSEC_PER_USEC);  in nmk_i2c_wait_xfer_done()  local
491 		wait_event_hrtimeout(priv->xfer_wq, priv->xfer_done, timeout);  in nmk_i2c_wait_xfer_done()
493 		unsigned long timeout = usecs_to_jiffies(priv->timeout_usecs);  in nmk_i2c_wait_xfer_done()  local
495 		wait_event_timeout(priv->xfer_wq, priv->xfer_done, timeout);  in nmk_i2c_wait_xfer_done()
498 	return priv->xfer_done;  in nmk_i2c_wait_xfer_done()
502  * read_i2c() - Read from I2C client device
503  * @priv: private data of I2C Driver
506  * This function reads from i2c client device when controller is in
507  * master mode. There is a completion timeout. If there is no transfer
508  * before timeout error is returned.
517 	writel(mcr, priv->virtbase + I2C_MCR);  in read_i2c()
520 	writel(readl(priv->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,  in read_i2c()
521 	       priv->virtbase + I2C_CR);  in read_i2c()
524 	i2c_set_bit(priv->virtbase + I2C_CR, I2C_CR_PE);  in read_i2c()
526 	init_waitqueue_head(&priv->xfer_wq);  in read_i2c()
527 	priv->xfer_done = false;  in read_i2c()
533 	if (priv->stop || !priv->vendor->has_mtdws)  in read_i2c()
540 	writel(readl(priv->virtbase + I2C_IMSCR) | irq_mask,  in read_i2c()
541 	       priv->virtbase + I2C_IMSCR);  in read_i2c()
546 		status = -ETIMEDOUT;  in read_i2c()
555 	for (count = (no_bytes - 2);  in fill_tx_fifo()
557 			(priv->cli.count != 0);  in fill_tx_fifo()
558 			count--) {  in fill_tx_fifo()
560 		nmk_i2c_writeb(priv, *priv->cli.buffer, I2C_TFR);  in fill_tx_fifo()
561 		priv->cli.buffer++;  in fill_tx_fifo()
562 		priv->cli.count--;  in fill_tx_fifo()
563 		priv->cli.xfer_bytes++;  in fill_tx_fifo()
569  * write_i2c() - Write data to I2C client.
570  * @priv: private data of I2C Driver
573  * This function writes data to I2C client
583 	writel(mcr, priv->virtbase + I2C_MCR);  in write_i2c()
586 	writel(readl(priv->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,  in write_i2c()
587 	       priv->virtbase + I2C_CR);  in write_i2c()
590 	i2c_set_bit(priv->virtbase + I2C_CR, I2C_CR_PE);  in write_i2c()
592 	init_waitqueue_head(&priv->xfer_wq);  in write_i2c()
593 	priv->xfer_done = false;  in write_i2c()
601 	if (priv->cli.count != 0)  in write_i2c()
605 	 * check if we want to transfer a single or multiple bytes, if so  in write_i2c()
609 	if (priv->stop || !priv->vendor->has_mtdws)  in write_i2c()
616 	writel(readl(priv->virtbase + I2C_IMSCR) | irq_mask,  in write_i2c()
617 	       priv->virtbase + I2C_IMSCR);  in write_i2c()
623 		dev_err(&priv->adev->dev, "write to slave 0x%x timed out\n",  in write_i2c()
624 			priv->cli.slave_adr);  in write_i2c()
625 		status = -ETIMEDOUT;  in write_i2c()
632  * nmk_i2c_xfer_one() - transmit a single I2C message
642 		priv->cli.operation = I2C_READ;  in nmk_i2c_xfer_one()
646 		priv->cli.operation = I2C_WRITE;  in nmk_i2c_xfer_one()
650 	if (status || priv->result) {  in nmk_i2c_xfer_one()
654 		i2c_sr = readl(priv->virtbase + I2C_SR);  in nmk_i2c_xfer_one()
657 			dev_err(&priv->adev->dev, "%s\n",  in nmk_i2c_xfer_one()
665 		status = status ? status : priv->result;  in nmk_i2c_xfer_one()
672  * nmk_i2c_xfer() - I2C transfer function used by kernel framework
682  * READ TRANSFER : We impose a restriction of the first message to be the
684  *		- a no index is coded as '0',
685  *		- 2byte big endian index is coded as '3'
689  *		eg. a I2C transation to read 2 bytes from index 0
691  *			msg[0].addr = client->addr;
696  *			msg[1].addr = client->addr;
702  * WRITE TRANSFER : The I2C standard interface interprets all data as payload.
705  *		eg. a I2C transation to write 2 bytes from index 1
726 	pm_runtime_get_sync(&priv->adev->dev);  in nmk_i2c_xfer()
730 		/* setup the i2c controller */  in nmk_i2c_xfer()
734 			priv->cli.slave_adr	= msgs[i].addr;  in nmk_i2c_xfer()
735 			priv->cli.buffer		= msgs[i].buf;  in nmk_i2c_xfer()
736 			priv->cli.count		= msgs[i].len;  in nmk_i2c_xfer()
737 			priv->stop = (i < (num_msgs - 1)) ? 0 : 1;  in nmk_i2c_xfer()
738 			priv->result = 0;  in nmk_i2c_xfer()
748 	pm_runtime_put_sync(&priv->adev->dev);  in nmk_i2c_xfer()
758  * disable_interrupts() - disable the interrupts
765 	writel(readl(priv->virtbase + I2C_IMSCR) & ~irq,  in disable_interrupts()
766 	       priv->virtbase + I2C_IMSCR);  in disable_interrupts()
771  * i2c_irq_handler() - interrupt routine
775  * This is the interrupt handler for the i2c driver. Currently
784 	struct device *dev = &priv->adev->dev;  in i2c_irq_handler()
790 	tft = readl(priv->virtbase + I2C_TFTR);  in i2c_irq_handler()
791 	rft = readl(priv->virtbase + I2C_RFTR);  in i2c_irq_handler()
794 	misr = readl(priv->virtbase + I2C_MISR);  in i2c_irq_handler()
802 		if (priv->cli.operation == I2C_READ) {  in i2c_irq_handler()
809 			fill_tx_fifo(priv, (MAX_I2C_FIFO_THRESHOLD - tft));  in i2c_irq_handler()
811 			 * if done, close the transfer by disabling the  in i2c_irq_handler()
814 			if (priv->cli.count == 0)  in i2c_irq_handler()
827 		for (count = rft; count > 0; count--) {  in i2c_irq_handler()
829 			*priv->cli.buffer = nmk_i2c_readb(priv, I2C_RFR);  in i2c_irq_handler()
830 			priv->cli.buffer++;  in i2c_irq_handler()
832 		priv->cli.count -= rft;  in i2c_irq_handler()
833 		priv->cli.xfer_bytes += rft;  in i2c_irq_handler()
838 		for (count = MAX_I2C_FIFO_THRESHOLD; count > 0; count--) {  in i2c_irq_handler()
839 			*priv->cli.buffer = nmk_i2c_readb(priv, I2C_RFR);  in i2c_irq_handler()
840 			priv->cli.buffer++;  in i2c_irq_handler()
842 		priv->cli.count -= MAX_I2C_FIFO_THRESHOLD;  in i2c_irq_handler()
843 		priv->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD;  in i2c_irq_handler()
849 		if (priv->cli.operation == I2C_READ) {  in i2c_irq_handler()
850 			while (!(readl(priv->virtbase + I2C_RISR)  in i2c_irq_handler()
852 				if (priv->cli.count == 0)  in i2c_irq_handler()
854 				*priv->cli.buffer =  in i2c_irq_handler()
856 				priv->cli.buffer++;  in i2c_irq_handler()
857 				priv->cli.count--;  in i2c_irq_handler()
858 				priv->cli.xfer_bytes++;  in i2c_irq_handler()
865 		if (priv->cli.count) {  in i2c_irq_handler()
866 			priv->result = -EIO;  in i2c_irq_handler()
868 				priv->cli.count);  in i2c_irq_handler()
871 		priv->xfer_done = true;  in i2c_irq_handler()
872 		wake_up(&priv->xfer_wq);  in i2c_irq_handler()
879 		priv->result = -EIO;  in i2c_irq_handler()
882 		i2c_set_bit(priv->virtbase + I2C_ICR, I2C_IT_MAL);  in i2c_irq_handler()
883 		priv->xfer_done = true;  in i2c_irq_handler()
884 		wake_up(&priv->xfer_wq);  in i2c_irq_handler()
898 		sr = readl(priv->virtbase + I2C_SR);  in i2c_irq_handler()
899 		priv->result = -EIO;  in i2c_irq_handler()
903 		i2c_set_bit(priv->virtbase + I2C_ICR, I2C_IT_BERR);  in i2c_irq_handler()
904 		priv->xfer_done = true;  in i2c_irq_handler()
905 		wake_up(&priv->xfer_wq);  in i2c_irq_handler()
916 		priv->result = -EIO;  in i2c_irq_handler()
920 		priv->xfer_done = true;  in i2c_irq_handler()
921 		wake_up(&priv->xfer_wq);  in i2c_irq_handler()
926 	/* unhandled interrupts by this driver - TODO*/  in i2c_irq_handler()
966 	clk_disable_unprepare(priv->clk);  in nmk_i2c_runtime_suspend()
977 	ret = clk_prepare_enable(priv->clk);  in nmk_i2c_runtime_resume()
987 		clk_disable_unprepare(priv->clk);  in nmk_i2c_runtime_resume()
1015 	if (of_property_read_u32(np, "clock-frequency", &priv->clk_freq))  in nmk_i2c_of_probe()
1016 		priv->clk_freq = I2C_MAX_STANDARD_MODE_FREQ;  in nmk_i2c_of_probe()
1019 	if (priv->clk_freq <= I2C_MAX_STANDARD_MODE_FREQ)  in nmk_i2c_of_probe()
1020 		priv->sm = I2C_FREQ_MODE_STANDARD;  in nmk_i2c_of_probe()
1022 		priv->sm = I2C_FREQ_MODE_FAST;  in nmk_i2c_of_probe()
1023 	priv->tft = 1; /* Tx FIFO threshold */  in nmk_i2c_of_probe()
1024 	priv->rft = 8; /* Rx FIFO threshold */  in nmk_i2c_of_probe()
1026 	/* Slave response timeout */  in nmk_i2c_of_probe()
1027 	if (!of_property_read_u32(np, "i2c-transfer-timeout-us", &timeout_usecs))  in nmk_i2c_of_probe()
1028 		priv->timeout_usecs = timeout_usecs;  in nmk_i2c_of_probe()
1030 		priv->timeout_usecs = 200 * USEC_PER_MSEC;  in nmk_i2c_of_probe()
1043 	struct device *dev = &priv->adev->dev;  in nmk_i2c_eyeq5_probe()
1044 	struct device_node *np = dev->of_node;  in nmk_i2c_eyeq5_probe()
1049 	priv->has_32b_bus = true;  in nmk_i2c_eyeq5_probe()
1055 		return -ENOENT;  in nmk_i2c_eyeq5_probe()
1057 	if (priv->clk_freq <= 400000)  in nmk_i2c_eyeq5_probe()
1059 	else if (priv->clk_freq <= 1000000)  in nmk_i2c_eyeq5_probe()
1075 	struct device_node *np = adev->dev.of_node;  in nmk_i2c_probe()
1076 	struct device *dev = &adev->dev;  in nmk_i2c_probe()
1078 	struct i2c_vendor_data *vendor = id->data;  in nmk_i2c_probe()
1079 	u32 max_fifo_threshold = (vendor->fifodepth / 2) - 1;  in nmk_i2c_probe()
1083 		return -ENOMEM;  in nmk_i2c_probe()
1085 	priv->vendor = vendor;  in nmk_i2c_probe()
1086 	priv->adev = adev;  in nmk_i2c_probe()
1087 	priv->has_32b_bus = false;  in nmk_i2c_probe()
1090 	if (of_device_is_compatible(np, "mobileye,eyeq5-i2c")) {  in nmk_i2c_probe()
1096 	if (priv->tft > max_fifo_threshold) {  in nmk_i2c_probe()
1098 			 priv->tft, max_fifo_threshold);  in nmk_i2c_probe()
1099 		priv->tft = max_fifo_threshold;  in nmk_i2c_probe()
1102 	if (priv->rft > max_fifo_threshold) {  in nmk_i2c_probe()
1104 			 priv->rft, max_fifo_threshold);  in nmk_i2c_probe()
1105 		priv->rft = max_fifo_threshold;  in nmk_i2c_probe()
1110 	priv->virtbase = devm_ioremap(dev, adev->res.start,  in nmk_i2c_probe()
1111 				      resource_size(&adev->res));  in nmk_i2c_probe()
1112 	if (!priv->virtbase)  in nmk_i2c_probe()
1113 		return -ENOMEM;  in nmk_i2c_probe()
1115 	priv->irq = adev->irq[0];  in nmk_i2c_probe()
1116 	ret = devm_request_irq(dev, priv->irq, i2c_irq_handler, 0,  in nmk_i2c_probe()
1120 				     "cannot claim the irq %d\n", priv->irq);  in nmk_i2c_probe()
1122 	priv->clk = devm_clk_get_enabled(dev, NULL);  in nmk_i2c_probe()
1123 	if (IS_ERR(priv->clk))  in nmk_i2c_probe()
1124 		return dev_err_probe(dev, PTR_ERR(priv->clk),  in nmk_i2c_probe()
1125 				     "could enable i2c clock\n");  in nmk_i2c_probe()
1129 	adap = &priv->adap;  in nmk_i2c_probe()
1130 	adap->dev.of_node = np;  in nmk_i2c_probe()
1131 	adap->dev.parent = dev;  in nmk_i2c_probe()
1132 	adap->owner = THIS_MODULE;  in nmk_i2c_probe()
1133 	adap->class = I2C_CLASS_DEPRECATED;  in nmk_i2c_probe()
1134 	adap->algo = &nmk_i2c_algo;  in nmk_i2c_probe()
1135 	adap->timeout = usecs_to_jiffies(priv->timeout_usecs);  in nmk_i2c_probe()
1136 	snprintf(adap->name, sizeof(adap->name),  in nmk_i2c_probe()
1137 		 "Nomadik I2C at %pR", &adev->res);  in nmk_i2c_probe()
1143 		 adap->name, priv->virtbase);  in nmk_i2c_probe()
1158 	i2c_del_adapter(&priv->adap);  in nmk_i2c_remove()
1163 	i2c_clr_bit(priv->virtbase + I2C_CR, I2C_CR_PE);  in nmk_i2c_remove()
1217 MODULE_DESCRIPTION("Nomadik/Ux500 I2C driver");